| Project/Area Number |
16500044
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hachinohe National College of Technology |
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Principal Investigator |
KUDOH Takao Hachinohe National College of Technology, Department of Electrical and Computer Engineering, Professor, 電気情報工学科, 教授 (10110214)
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| Co-Investigator(Kenkyū-buntansha) |
KUJI Norio Hachinohe National College of Technology, Department of Electrical and Computer Engineering, Professor, 電気情報工学科, 教授 (80369909)
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| Project Period (FY) |
2004 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2006: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 2005: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 2004: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Keywords | VLSI / Logic-in-Memory / Allocation / Scheduling / Mobility / High-Level-Synthesis / ハイレベルシンセシス / 最適設計 / 最適設計問題 |
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| Research Abstract |
One of the most serious problem in recent VLSI system is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processor is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfers between adjacent modules are done simply in a single clock period by a shift-register chain.
A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of a chip area. That is, we consider the best scheduling together with allocation such that the processing time become minimum under a constraint of a fixed number of modules. A genetic algorithm and a heuristic algorithm are proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.
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