| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2005: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2004: ¥2,200,000 (Direct Cost: ¥2,200,000)
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| Research Abstract |
Reconfigurable computing is computer processing with highly flexible computing fabrics. In the last decade there was a renaissance in this area of research with many proposed reconfigurable architectures developed. Most of these have a two-dimensional logic block array architecture, and they have a memory that stores two or more contexts. These devices support run-time reconfiguration by rapidly switching between contexts. However, in compared with ASIC, dynamic reconfigurable devices are generally not considered to be power efficient because they use a large number of transistors to provide programmability. Large power consumption therefore becomes a constraining factor in device design. Power optimization has attracted increase attention due to the rapid growth of personal wireless communications, battery powered devices and portable digital applications.
It is our aim to reduce the power consumption using dynamic reconfiguration. The dynamic reconfigurable devices enable us to reconf
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igure circuits according to the current usage conditions. We designed smaller circuits that may be omitted if their function is not used at some point in time in the original circuit. We expected that energy savings could be realized by reconfiguration of these smaller circuits, since the energy consumption of the smaller circuits is usually low.
In this project, we estimate the energy consumption in the operation and reconfiguration of the circuits. Then, the energy consumption of the smaller circuits is compared with that of the original circuit. We show that execution with reconfiguration the smaller circuits reduces the energy consumption. The energy consumption was reduced by an average of about 71% in the case of matching circuit, and a maximum of about 35% for FIR filters. Moreover, the operating frequency of the smaller circuits is higher than original circuit.
However, it is difficult to design smaller circuits that are suitable for various applications. We propose a unique technique to making smaller circuits based on logic gate reduction. The basic idea of this technique is that logic gates are reducible if the input is set to a constant. The resulting circuits are called data-dependent circuits. We design the data-dependent circuits and reconfigure them in accordance with the conditions of usage ; self-reconfiguration is also possible. We apply our method to a DCT module of JPEG encoder. As a result of evaluation, the energy consumption was reduced by a maximum of about 16.5%. Less
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