| Project/Area Number |
16560305
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Hokkaido Institute of Technology |
|---|
Principal Investigator |
FUJINAGA Kiyohisa Hokkaido Institute of Technology, Department of Engineering, Professor, 工学部, 教授 (40285515)
|
|---|
| Project Period (FY) |
2004 – 2006
|
| Project Status |
Completed (Fiscal Year 2006)
|
| Budget Amount *help |
¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2006: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2005: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2004: ¥800,000 (Direct Cost: ¥800,000)
|
|---|
| Keywords | SiGe / SOI / MOSFET / Quantum Well / Buried Channel / Hole Mobility / SIMOX / ダブルチャネル / サブスレッショルド特性 / CVD / MOSFET / 電界効果デバイス / 転位密度 / 正孔 / 移動度 |
|---|
| Research Abstract |
The effective hole mobility of SiGe buried-channel MOSTFT on SOI depends on the SiGe channel structure as well as the crystalline quality. In this work, the two sorts of buried-channel structure that consisted of single quantum well (SQW) and triple quantum wells (TQW) were formed at 550℃ on SIMOX wafers by low-pressure CVD. The growth apparatus was built on the basis of ultra-clean technology. The Ge composition of the alloy was 0.2. The SiGe well width, Lz, was 13 nm for SQW and fixed at 3 nm for TQW. The Si barrier thickness, LB, was 2 and 8 nm for TQW. The MOSFETs with the 5.9 nm gate oxide were fabricated on the layers. The Effective hole mobility, μeff, versus effective electric field, Eeff, for the both device types were obtained at room temperature. The mobility of TQW devices was enhanced nearly by 60 %, compared with that for the SQW devices. The mobility enhancement might be due to the increase of the number of holes trapped in the SiGe quantum wells that had the high hole mobility. The best effective hole mobility was obtained for the triple quantum wells channel device with the 3-nm SiGe well width and 2-nm Si barrier thickness fabricated on 40-nm-thick SOI. It was concluded that the multiple quantum wells channel pMOSFETs on SOI enhanced the effective hole mobility and promoted the device performance.
|
