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Study of basic characteristics and application of Non-volatile Memory

Research Project

Project/Area Number 16560311
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionWaseda University

Principal Investigator

YOSHIHARA Tsutomu  Waseda University, Graduate School of Information, Production, and Systems, Professor, 大学院・情報生産システム研究科, 教授 (60367175)

Project Period (FY) 2004 – 2006
Project Status Completed (Fiscal Year 2006)
Budget Amount *help
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2006: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 2005: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 2004: ¥1,900,000 (Direct Cost: ¥1,900,000)
KeywordsNon-Volatile Memory / MRAM / sensing Sheme / Dual-Port / 電子デバイス・集積回路 / 回路設計・CAD / 記憶・記録
Research Abstract

We propose a pipe-lined selfreference read scheme of MRAM with read modify write which can make an operation period short. It also brings continuous read out accompanied with a mixed mat architecture. A new self-reference sense amplifier supported by a voltage transferred circuit has a wide margin. It is able to tolerate 50% MTJ resistance variation for sensing operation, and makes 75MHz operation at 1.2V Vcc possible. It brings a robust memory module for embedded memory system and suits mobile/robotics synchronous memory system.
We proposed two kinds of implementation of the DP-MRAM, one (RWDP) is for read/write concurrent operation, while another (R2DP)enables simultaneous read operation in addition to the above read/write concurrent operation. For the simultaneous read case with the bitline clamped by a 0VVref, the high speed operation is realized. Besides this, a swing-less bit-line sensing (SLBS) technique makes read period much shorter and keeps the operation frequency as same as the single port MRAM. From simulation we can see that the data can be successfully recognized with enough margin by sense amplifier under the conditions of Vcc=1.0V and the operation frequency of 100MHz. With the advantage in chip density it can be used as anavailable implementation to replace the SRAM in the application of cache memory area.

Report

(4 results)
  • 2006 Annual Research Report   Final Research Report Summary
  • 2005 Annual Research Report
  • 2004 Annual Research Report
  • Research Products

    (9 results)

All 2006 2005 2004

All Journal Article (9 results)

  • [Journal Article] A 100MHz MRAM implementation with simultaneous operation function and high chip density2006

    • Author(s)
      Hu Li, Leona Okamura, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara
    • Journal Title

      ISCIT2006

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] MRAMに適したセルフリファレンス型センス手法の検討2006

    • Author(s)
      岡村怜王奈, 木原雄二, 金泰潤, 木村史法, 松井悠亮, 大石司, 吉原務
    • Journal Title

      信学技報 Vol.106 No.2

      Pages: 55-60

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A 100MHz MRAM implementation with simultaneous operation function and high chip density2006

    • Author(s)
      Hu Li, Leona Okamura, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara
    • Journal Title

      ISCIT

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A 75MHz MRAM with Pipe-Lined Self-Reference Read Scheme for Mobile/Robotics Memory System2005

    • Author(s)
      Tae Yun Kim, Fuminori Kimura, Yusuke Matsui, Tsutomu Yoshihara, Tsukasa Ooishi, Yuji Kihara, Masahiro Hatanaka
    • Journal Title

      ASSCC

    • NAID

      110004718927

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] MRAMメモリセルを用いたデュアルポートメモリの検討2005

    • Author(s)
      松井, 岡村, 大石, 吉原
    • Journal Title

      電気関係学会九州支部連合大会

      Pages: 162-162

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories2005

    • Author(s)
      K.Furutani, T.Hamamoto, T.Miki, M.Nakano, T.Yoshihara
    • Journal Title

      IEICE TRANS.ELECTRON VOL.E88-C, No.2

      Pages: 255-263

    • NAID

      110003215116

    • Related Report
      2004 Annual Research Report
  • [Journal Article] A Cost-Efficient High Performance Dynamic TCAM With Pipelined Hierarchical Searching and Shift Redundancy Architecture2005

    • Author(s)
      H.Noda, T.Yoshihara et al.
    • Journal Title

      IEEE Journal of Solid-State Circuits Vol.40 No.1 Jan

      Pages: 245-253

    • Related Report
      2004 Annual Research Report
  • [Journal Article] A 312-MHz 16-Mb Random-Cycle Embedded DRAM Macro With a Power-Down Data Retention Mode for Mobile Applications2005

    • Author(s)
      F.Morishita, T.Yoshihara et al.
    • Journal Title

      IEEE Journal of Solid-State Circuites Vol.40, No.1, Jan

      Pages: 204-205

    • Related Report
      2004 Annual Research Report
  • [Journal Article] MRAMに適したセルフリファレンス型センス手法の検討2004

    • Author(s)
      米田健司, 大石司, 吉原務
    • Journal Title

      電気関係学会九州支部連合大会

      Pages: 310-310

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary

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Published: 2004-04-01   Modified: 2016-04-21  

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