| Project/Area Number |
16560311
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Waseda University |
|---|
Principal Investigator |
YOSHIHARA Tsutomu Waseda University, Graduate School of Information, Production, and Systems, Professor, 大学院・情報生産システム研究科, 教授 (60367175)
|
|---|
| Project Period (FY) |
2004 – 2006
|
| Project Status |
Completed (Fiscal Year 2006)
|
| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2006: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 2005: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 2004: ¥1,900,000 (Direct Cost: ¥1,900,000)
|
|---|
| Keywords | Non-Volatile Memory / MRAM / sensing Sheme / Dual-Port / 電子デバイス・集積回路 / 回路設計・CAD / 記憶・記録 |
|---|
| Research Abstract |
We propose a pipe-lined selfreference read scheme of MRAM with read modify write which can make an operation period short. It also brings continuous read out accompanied with a mixed mat architecture. A new self-reference sense amplifier supported by a voltage transferred circuit has a wide margin. It is able to tolerate 50% MTJ resistance variation for sensing operation, and makes 75MHz operation at 1.2V Vcc possible. It brings a robust memory module for embedded memory system and suits mobile/robotics synchronous memory system.
We proposed two kinds of implementation of the DP-MRAM, one (RWDP) is for read/write concurrent operation, while another (R2DP)enables simultaneous read operation in addition to the above read/write concurrent operation. For the simultaneous read case with the bitline clamped by a 0VVref, the high speed operation is realized. Besides this, a swing-less bit-line sensing (SLBS) technique makes read period much shorter and keeps the operation frequency as same as the single port MRAM. From simulation we can see that the data can be successfully recognized with enough margin by sense amplifier under the conditions of Vcc=1.0V and the operation frequency of 100MHz. With the advantage in chip density it can be used as anavailable implementation to replace the SRAM in the application of cache memory area.
|
