| Budget Amount *help |
¥16,770,000 (Direct Cost: ¥12,900,000、Indirect Cost: ¥3,870,000)
Fiscal Year 2019: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2018: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2017: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2016: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
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| Outline of Final Research Achievements |
In this research, we worked on developing a high-speed system that emulates the behavior of a large-scale many-core processor with thousands of cores while maintaining cycle-level accuracy using FPGA. This system accelerates research and development of many-core architecture and research and development of system software and application programs for many-core processors. Focusing on the RISC-V architecture, attracting attention because of its open architecture, we implemented an efficient scalar processor with a typical five-stage pipelining and its development environment. We released their source code as open source.
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