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Heterogeneous Wireless Communication Processor Based on Low-Power Self-Timed Circuits

Research Project

Project/Area Number 16K00082
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system
Research InstitutionKochi University of Technology

Principal Investigator

IWATA Makoto  高知工科大学, 情報学群, 教授 (60232683)

Project Period (FY) 2016-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2018: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2017: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2016: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Keywordsヘテロジニアス無線通信 / セルフタイム回路 / データ駆動 / ストリーム処理 / 変復調 / FFT / 計算機アーキテクチャ / 無線通信 / 実時間処理 / 計算機システム
Outline of Final Research Achievements

This research aimed to establish how to construct a heterogeneous wireless communication processor that can be adapted to multiple wireless communication systems, which will be essential for future wireless communication environments that integrate wide area, wireless LAN, and millimeter wave lines. In the research, we targeted modulation, error correction and MAC functions embedded in multi-mode receivers of multi-user MIMO system and studied (1) pipeline parallel algorithms of them, (2) stream signal processing architecture that can process them in parallel, and (3) low-power self-timed pipeline STP circuit implementation of dedicated engine to configure them. These basic techniques were revealed and published as several academic papers.

Academic Significance and Societal Importance of the Research Achievements

本研究の成果は、セルフタイム回路を基盤として、複数の異速度信号ストリームを多重に処理可能なプロセッサを構成することによって、WPAN、WLAN、MBWA等の無線信号ストリームを円滑に多重処理可能なシステムを実現できる見通しを得られたことである。これによって、異種の無線に対応したチップ/回路モジュールを組み合わせた複雑なハードウェア構成ではなく、本提案のように均質なアーキテクチャで多重処理が可能になるヘテロジニアス無線通信プロセッサを実現できる点に学術的意義がある。これによって、将来的には、無線通信システムの設計・製造コストの低減や信頼性の向上にも寄与することが期待できる点に社会的意義がある。

Report

(5 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • 2017 Research-status Report
  • 2016 Research-status Report
  • Research Products

    (7 results)

All 2020 2019 2018 2017

All Presentation (7 results) (of which Int'l Joint Research: 7 results)

  • [Presentation] Pipeline Stage Level Simulation Method for Self-Timed Data-Driven Processor on FPGA2020

    • Author(s)
      Senri YOSHIOKA, Shuji SANNOMIYA, Makoto IWATA, and Hiroaki NISHIKAWA
    • Organizer
      The 2020 International Electrical Engineering Congress
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Area-Efficient FPGA Implementation of Self-Timed Data-Driven Processor2019

    • Author(s)
      Kanji NAGANO and Makoto IWATA
    • Organizer
      The 7th International Symposium on Frontier Technology
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Application-Oriented LPWA Network with A Moving Gateway and Stationary End-Nodes2019

    • Author(s)
      Kenta KUSUDA and Makoto IWATA
    • Organizer
      A premier international technical conference of IEEE Region 10
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Decentralized Hardware Scheduler for Self-Timed Data-Driven Multiprocessor2018

    • Author(s)
      Kazuma Fukuda, Yushin Wada, and Makoto Iwata
    • Organizer
      2018 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'18)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Least Slack Time Hardware Scheduler Based on Self-Timed Data-Driven Processor2018

    • Author(s)
      Yushin Wada, Kazuma Fukuda, and Makoto Iwata
    • Organizer
      2018 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'18)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Priority-Based Hardware Scheduler for Self-Timed Data-Driven Processor2017

    • Author(s)
      Kazuma FUKUDA, Hiroki SHIBUTA, and Makoto IWATA
    • Organizer
      International Conference on Parallel and Dstributed Processing Techniques and Applications
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] Pipelined FP Array for Stream-Driven Image Processor2017

    • Author(s)
      Masahiro TABARA, Hiroki SHIBUTA, and Makoto IWATA
    • Organizer
      International Conference on Parallel and Dstributed Processing Techniques and Applications
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research

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Published: 2016-04-21   Modified: 2021-02-19  

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