A Framework for FPGA-based Accelerators with Maximum Memory Performance

• Project/Area Number: 16K16026
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Hokkaido University
• Principal Investigator: Takamaeda Shinya 北海道大学, 情報科学研究科, 准教授 (60738897)
• Project Period (FY): 2016-04-01 – 2018-03-31
• Project Status: Completed (Fiscal Year 2017)
• Budget Amount: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000); Fiscal Year 2017: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000); Fiscal Year 2016: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
• Keywords: FPGA / 高位合成 / Python / コンパイラ / 深層学習 / ディープニューラルネットワーク / 計算機システム

Outline of Final Research Achievements

We developed a multi-paradigm high-level hardware design framework that easily exploits on-chip memory blocks and memory bandwidth of an FPGA. The framework is based on Veriloggen, a Python-based domain-specific language for hardware design. The newly developed framework supports 3 different programming paradigms; The compiler supports Sequential, Stream, and RTL. In addition to the framework, we developed a highly-abstracted dataflow-based hardware compiler for deep neural networks.

Research Products

• [Journal Article] A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing (2018)
  • Author(s): Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, and Yasuhiko Nakashima
  • Journal Title: IEICE TRANSACTIONS on Information and Systems Volume: Vol.E101-D Pages: 288-302
  • Peer Reviewed
• [Journal Article] Japanese High-level Synthesis Tools for FPGA Hardware Acceleration (2017)
  • Author(s): 渡邊 実, 佐野 健太郎, 高前田 伸也, 三好 健文, 中條 拓伯
  • Journal Title: 電子情報通信学会論文誌B 通信 Volume: J100-B Issue: 1 Pages: 1-10
  • DOI: 10.14923/transcomj.2016JBI0002
  • ISSN: 1881-0209
  • Year and Date: 2017-01-01
  • Peer Reviewed
• [Presentation] CPRring: A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing (2017)
  • Author(s): Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, and Yasuhiko Nakashima
  • Organizer: The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2017)
  • Place of Presentation: Napa, CA, USA
  • Year and Date: 2017-04-30
  • Int'l Joint Research
• [Presentation] A Multi-Level Power-Capping Mechanism for FPGAs (2017)
  • Author(s): Keisuke Fujimoto, Takashi Nakada, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima
  • Organizer: The 1st. cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2017)
• [Presentation] A Structure-aware Ring-based Checkpointing Architecture for FPGA Computing (2017)
  • Author(s): Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, and Yasuhiko Nakashima: CPRring
  • Organizer: The 25th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM2017)
• [Presentation] Energy-Efficient In-Memory Neural Network Processor, (2017)
  • Author(s): Shinya Takamaeda-Yamazaki
  • Organizer: 17th International Forum on MPSoC for Software-defined Hardware (MPSoC 2017)
  • Int'l Joint Research / Invited
• [Presentation] アルゴリズムとハードウェアの協調設計による新時代コンピューティング (2017)
  • Author(s): 高前田 伸也
  • Organizer: 電子情報通信学会集積回路研究会(IEICE-ICD)
  • Invited
• [Presentation] アルゴリズムとハードウェアの協調設計によるディープラーニングアクセラレーション (2017)
  • Author(s): 高前田 伸也
  • Organizer: Design Solution Forum 2017
  • Invited
• [Presentation] Accelerating Deep Learning by Hardware/Algorithm Co-Design (2017)
  • Author(s): Shinya Takamaeda-Yamazaki
  • Organizer: International Workshop on Advances in Networking and Computing (WANC 2017)
  • Int'l Joint Research / Invited
• [Presentation] kebe, Tetsuya Asai, and Masato Motomura: A Time-Division Multiplexing Ising Machine on FPGAs (2017)
  • Author(s): Kasho Yamamoto, Huang Weiqiang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, and Masato Motomura
  • Organizer: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017)
  • Int'l Joint Research
• [Presentation] メモリアクセスパターンを考慮した遅延評価によるZDD構築の高速化 (2017)
  • Author(s): 熊澤 輝顕, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人
  • Organizer: 第 30回回路とシステムワークショップ, 於 北九州国際会議場
• [Presentation] ゆるふわコンピュータ (2017)
  • Author(s): 高前田 伸也
  • Organizer: 情報処理学会第79回全国大会IPSJ-ONE
  • Place of Presentation: 名古屋大学
  • Invited
• [Presentation] CPRtree: A Tree-based Checkpointing Architecture for Heterogeneous FPGA Computing (2016)
  • Author(s): Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima
  • Organizer: 4th International Symposium on Computing and Networking (CANDAR 2016)
  • Place of Presentation: Higashi-Hiroshima, Hiroshima, Japan
  • Year and Date: 2016-11-22
  • Int'l Joint Research
• [Presentation] Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs (2016)
  • Author(s): Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, and Yasuhiko Nakashima
  • Organizer: 4th International Symposium on Computing and Networking (CANDAR 2016)
  • Place of Presentation: Higashi-Hiroshima, Hiroshima, Japan
  • Year and Date: 2016-11-22
  • Int'l Joint Research
• [Presentation] ハードウェアはやわらかい (2016)
  • Author(s): 高前田 伸也
  • Organizer: 第15回情報科学技術フォーラム (FIT 2016) 助教が吼える！各界の若手研究者大集合
  • Place of Presentation: 富山大学
  • Year and Date: 2016-09-07
  • Invited
• [Presentation] Customizable Hardware Abstraction (2016)
  • Author(s): Shinya Takamaeda-Yamazaki
  • Organizer: 16th International Forum on MPSoC for Software-defined Hardware (MPSoC 2016)
  • Place of Presentation: Nara Hotel, Nara, Nara, Japan
  • Year and Date: 2016-07-11
  • Int'l Joint Research / Invited
• [Presentation] Pythonによるカスタム可能な高位設計技術 (2016)
  • Author(s): 高前田 伸也
  • Organizer: Design Solution Forum 2016
  • Place of Presentation: 新横浜国際ホテル
  • Invited
• [Remarks] Veriloggen
  • URL: https://github.com/PyHDI/veriloggen