Stacked short channel III-V MOSFET
| Project/Area Number |
16K18087
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
Kanazawa Toru 東京工業大学, 工学院, 助教 (40514922)
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| Project Period (FY) |
2016-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2017: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2016: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
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| Keywords | MOSFET / 化合物半導体 / MOCVD / マルチゲート / ナノシート / III-V族化合物 / MOSトランジスタ / マルチゲート構造 / 高移動度チャネル / 結晶成長 |
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| Outline of Final Research Achievements |
A transistor with vertically stacked InGaAs nanosheet channel was studied to realize the high-speed and low-power logic circuits. We proposed and demonstrated the fabrication process of InGaAs nanosheet channels, which were suspended by the heavily doped source/drain regrown by MOCVD. The cross-sectional observation showed that the two stacked InGaAs nanosheets had the thickness of 10 nm and width of 100 nm. After the formation of gate stacks with the high-k dielectric and molybdenum electrode, the transistor properties were measured. The I-V characteristics indicated the advantages of the stacked nanosheet structure.
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Report
(3 results)
Research Products
(4 results)
