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Development of fully autonomous error-correctable VLSI design technology and its application to brain-inspired LSI system

Research Project

Project/Area Number 16KT0187
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section特設分野
Research Field Intensification of Artifact Systems
Research InstitutionTohoku University

Principal Investigator

NATSUI Masanori  東北大学, 電気通信研究所, 准教授 (10402661)

Research Collaborator HANYU Takahiro  
Project Period (FY) 2016-07-19 – 2019-03-31
Project Status Completed (Fiscal Year 2018)
Budget Amount *help
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2017: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2016: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Keywords集積回路 / LSI設計技術 / ディペンダブルコンピューティング / 誤り訂正技術 / 最適化アルゴリズム / ディペンダブル・コンピューティング
Outline of Final Research Achievements

In this research, we conducted the research toward the realization of post-process oriented design technology which is based on the concept of adjusting the circuit operating point according to the process variation effect occurred after fabrication, instead of the conventional approach of assigning sufficient operation margin. As a concrete approach, we conducted the design of high-performance and highly-reliable next-generation VLSI that implements the above functions compactly by combining semiconductor device technology and spintronics device technology. Specifically, we promoted research toward establishing a design technology for the realization of next-generation VLSI with plasticity, which has the property of changing its structure and operation dynamically and autonomously in response to the operation environment.

Academic Significance and Societal Importance of the Research Achievements

本研究成果を基盤とする設計技術により,高い性能が得られる可能性を有しつつも微細プロセスの高バラつき条件下においては実用に耐えないとされてきた様々な回路設計技術を,高性能VLSI実現の手段の一つとして再び活用できるようになる.これは設計における適用技術の選択肢を広げ,高性能VLSIの実現をより容易にすることにもつながる.すなわち,本技術は,単にバラつきの影響を抑え,回路性能を保証するためだけの技術ではなく,最先端プロセスが有する性能を設計者が最大限に活用できる環境を与え,従来技術では成し得ない十分な柔軟性・信頼性を有するVLSIをより容易に設計可能にする重要な技術といえる.

Report

(4 results)
  • 2018 Annual Research Report   Final Research Report ( PDF )
  • 2017 Research-status Report
  • 2016 Research-status Report
  • Research Products

    (29 results)

All 2019 2018 2017 2016 Other

All Int'l Joint Research (1 results) Journal Article (5 results) (of which Peer Reviewed: 5 results,  Open Access: 2 results,  Acknowledgement Compliant: 1 results) Presentation (23 results) (of which Int'l Joint Research: 13 results,  Invited: 6 results)

  • [Int'l Joint Research] トロント大学(カナダ)

    • Related Report
      2017 Research-status Report
  • [Journal Article] Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware2019

    • Author(s)
      Natsui Masanori、Chiba Tomoki、Hanyu Takahiro
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 58 Issue: SB Pages: SBBB01-SBBB01

    • DOI

      10.7567/1347-4065/aafb4d

    • NAID

      210000135331

    • Related Report
      2018 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design of MTJ-Based nonvolatile logic gates for quantized neural networks2018

    • Author(s)
      Natsui Masanori、Chiba Tomoki、Hanyu Takahiro
    • Journal Title

      Microelectronics Journal

      Volume: 82 Pages: 13-21

    • DOI

      10.1016/j.mejo.2018.10.005

    • Related Report
      2018 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit2018

    • Author(s)
      M. Natsui and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 57/4S Issue: 4S Pages: 04FN03-04FN03

    • DOI

      10.7567/jjap.57.04fn03

    • NAID

      210000148986

    • Related Report
      2017 Research-status Report
    • Peer Reviewed
  • [Journal Article] Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction2017

    • Author(s)
      M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 56 Issue: 4S Pages: 04CN01-04CN01

    • DOI

      10.7567/jjap.56.04cn01

    • Related Report
      2016 Research-status Report
    • Peer Reviewed / Open Access / Acknowledgement Compliant
  • [Journal Article] Design of a Variation-Resilient Single-Ended Nonvolatile 6-Input Lookup Table Circuit with a Redundant-MTJ-Based Active Load for Smart IoT Applications2017

    • Author(s)
      D. Suzuki, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu
    • Journal Title

      IET Electronics Letters

      Volume: 53 Issue: 7 Pages: 456-458

    • DOI

      10.1049/el.2016.4233

    • Related Report
      2016 Research-status Report
    • Peer Reviewed / Open Access
  • [Presentation] Impact of MTJ-Based Nonvolatile Microcontroller LSI for IoT Applications2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, H. Sato, S. Ikeda, T. Endoh, and T. Hanyu
    • Organizer
      5th CIES Technology Forum / DAY 1 International Symposium
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] MTJ-Based Nonvolatile Logic Gates for Quantized Neural Network Hardware2019

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      The 6th International Symposium on Brainware LSI
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
    • Organizer
      2019 IEEE International Solid-State Circuits Conference (ISSCC2019)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui
    • Organizer
      IEEE SSCS Kansai Chapter Technical Seminar
    • Related Report
      2018 Annual Research Report
    • Invited
  • [Presentation] MTJ-Based Nonvolatile Ternary Logic Gate for Quantized Convolutional Neural Networks2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] MTJ-Based Nonvolatile Logic Gate for Binarized Convolutional Neural Networks and Its Impact2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      2018 International Conference on Solid State Devices and Materials (SSDM2018)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Systematic Intrusion Detection Technique for In-Vehicle Network Based on Time-Series Feature Extraction2018

    • Author(s)
      H. Suda, M. Natsui, and T. Hanyu
    • Organizer
      48th IEEE International Symposium on Multiple-Valued Logic (ISMVL2018)
    • Related Report
      2018 Annual Research Report 2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] 不揮発量子化ニューラルネットワーク構造に基づく小型・超低消費電力XNOR回路の構成2018

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      平成30年度電気関係学会東北支部連合大会
    • Related Report
      2018 Annual Research Report
  • [Presentation] MTJベースばらつき補正機能を用いた2値化ニューラルネットワーク向け低消費電力・省面積bitcount回路の構成2018

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      第32回多値論理とその応用研究会
    • Related Report
      2018 Annual Research Report
  • [Presentation] MTJ-Based Nonvolatile Logic LSI for Ultra Low-Power and Highly Dependable Computing2018

    • Author(s)
      M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
    • Organizer
      China Semiconductor Technology International Conference (CSTIC)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Data-Stream-Aware Computing for Highly Dependable VLSI Systems2018

    • Author(s)
      M. Natsui, H. Suda and T. Hanyu
    • Organizer
      The 5th International Symposium on Brainware LSI
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] 次世代IoT社会に向けた脳型LSI設計技術2018

    • Author(s)
      夏井雅典
    • Organizer
      電子情報通信学会 総合大会
    • Related Report
      2017 Research-status Report
    • Invited
  • [Presentation] 脳型計算に基づく非シグネチャ不正侵入検出手法2018

    • Author(s)
      須田拓樹,夏井雅典,羽生貴弘
    • Organizer
      第31回多値論理とその応用研究会
    • Related Report
      2017 Research-status Report
  • [Presentation] 適切な通信ネットワークのトラフィックを考慮した高機能・低コストエッジプロセッサの構成に関する一考察2017

    • Author(s)
      加藤健太郎,夏井雅典,羽生貴弘
    • Organizer
      第30回多値論理とその応用研究会
    • Place of Presentation
      石川県金沢市
    • Year and Date
      2017-01-07
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] Energy-Efficient Data-Access Technique for an Ultra Low-Power Nonvolatile Microcontroller Unit2017

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      3rd ImPACT International Symposium on Spintronic Memory, Circuit and Storage
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] Energy-Efficient High-Performance Nonvolatile VLSI Processor with a Temporary-Data Reuse Technique2017

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      Extended Abstracts of 2017 International Conference on Solid State Devices and Materials (SSDM2017)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] 時系列特徴を用いたチップ内データ転送エラー訂正手法とその可能性2017

    • Author(s)
      加藤健太郎,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2017 -VLSI設計の新しい大地-
    • Related Report
      2017 Research-status Report
  • [Presentation] 時系列特徴を用いた脳型計算ベース車載ネットワークセキュリティ技術2017

    • Author(s)
      夏井雅典,須田拓樹,羽生貴弘
    • Organizer
      多値論理研究ノート
    • Related Report
      2017 Research-status Report
  • [Presentation] 脳型LSIを拓く集積回路・アーキテクチャの展望2017

    • Author(s)
      夏井雅典
    • Organizer
      VLSI夏の学校「LSI技術者のための人工知能基礎講座」
    • Related Report
      2017 Research-status Report
    • Invited
  • [Presentation] 脳型計算に基づく車載ネットワークの不正侵入検出法2017

    • Author(s)
      須田拓樹,夏井雅典,羽生貴弘
    • Organizer
      平成29年度電気関係学会東北支部連合大会
    • Related Report
      2017 Research-status Report
  • [Presentation] 時系列特徴を考慮した脳型計算ベース車載ネットワークセキュリティ技術に関する基礎的検討2017

    • Author(s)
      須田拓樹,夏井雅典,羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2017
    • Related Report
      2017 Research-status Report
  • [Presentation] Towards Ultra Low-Power and Highly Dependable VLSI Computing Based on MTJ-Based Nonvolatile Logic-in-Memory Architecture2016

    • Author(s)
      M. Natsui, T. Endoh, H. Ohno, and T. Hanyu
    • Organizer
      BIT's 6th Annual World Congress of Nano Science & Technology 2016
    • Place of Presentation
      シンガポール
    • Year and Date
      2016-10-26
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme2016

    • Author(s)
      M. Natsui, A. Tamakoshi, T. Endoh, H. Ohno, and T. Hanyu
    • Organizer
      2016 International Conference on Solid State Devices and Materials
    • Place of Presentation
      茨城県つくば市
    • Year and Date
      2016-09-26
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research

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Published: 2016-07-20   Modified: 2023-03-08  

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