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Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration Theory

Research Project

Project/Area Number 17300009
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionTohoku University

Principal Investigator

KAMEYAMA Michitaka  Tohoku University, Graduate School of Information Sciences, Professor (70124568)

Co-Investigator(Kenkyū-buntansha) HARIYAMA Masanori  Graduate School of Information Sciences, 大学院・情報科学研究科, Associate Professor (10292260)
Project Period (FY) 2005 – 2007
Project Status Completed (Fiscal Year 2007)
Budget Amount *help
¥13,400,000 (Direct Cost: ¥12,200,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2007: ¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2006: ¥4,300,000 (Direct Cost: ¥4,300,000)
Fiscal Year 2005: ¥3,900,000 (Direct Cost: ¥3,900,000)
KeywordsSystem-on-Chip / High-level Synthesis / Reconfigurable VLSI / Highly-Safe Intelligent Vehicle / Motion Estimation / Road Extraction / Vehicle Extraction / Human Extraction / ステレオビジョン / メモリアロケーション / 非同期アーキテクチャ / ベイジアンネットワーク / VLSIアーキテクチャ / システムレベル統合設計 / サンプリング周期
Research Abstract

Intelligent algorithms, advanced VLSI architectures and a system integration theory are studied to develop a highly-safe intelligent vehicle.
(1) System-Application-Level Design Theory
A real-world intelligent integrated system consists of three basic modules of environment recognition, prediction or estimation, and behavior planning. A system integration theory including derivation of performance specification is studied to bridge the gap between the various design levels as well as their VLSI-oriented intelligent algorithms.
(2) Processing Module for Highly-Safe Intelligent Vehicles
VLSI-oriented algorithms for road extraction, vehicle extraction and human extraction using 3-dimensional image information are developed. Moreover, motion estimation of a vehicle is done based on Bayesian Network The problem is equivalent to estimation of a driver's intention. The driver's intentions are hierarchically defined, so that the designed Bayesian Network becomes as simple as possible. Then, causal relation between the intentions is discussed to reflect the real-world motion process.
(3) Optimal Design Theory of VLSI Processors for Intelligent Integrated Systems
To achieve power minimization under a time/area constraint, high-level synthesis techniques are investigated based on scheduling and allocation. One typical example is a parallel VLSI for 3-dimensional image processing with optimal memory allocation which solves the data transfer bottleneck between processing elements and memory modules.
(4) Reconfigurable VLSI Computing
Fine-grained reconfigurable VLSIs for real-world applications superior to the conventional FPGAs are designed and implemented based on new architectures such as direct allocation of a control-data-flow graph, a bit-serial arithmetic operation, a dynamic control of power dissipation, and a logic-in-memory architecture utilizing nonvolatile devices.

Report

(4 results)
  • 2007 Annual Research Report   Final Research Report Summary
  • 2006 Annual Research Report
  • 2005 Annual Research Report
  • Research Products

    (85 results)

All 2007 2006 2005

All Journal Article (85 results) (of which Peer Reviewed: 24 results)

  • [Journal Article] ウィンドウ演算のための最適スケジューリング・メモリアロケーション2007

    • Author(s)
      小林康浩, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会論文誌 Vol.J90-D,No.5

      Pages: 1178-1193

    • NAID

      110007380712

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture2007

    • Author(s)
      Masanori Hariyama, Shota Ishihara, Chang Chia Wei and Michitaka Kameyama
    • Journal Title

      IEEE Asian Solid-State Circuits Conference

      Pages: 380-383

    • NAID

      110006546969

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Design of a Multi-Context FPVLSI based on an AsynchronousBit-Serial Architecture2007

    • Author(s)
      Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
    • Journal Title

      Sixth IEEE Dallas Circuits and SystemsWorkshop

      Pages: 59-62

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] 相互結合網簡単化を考慮した遺伝的アルゴリズムに基づく電源・しきい値電圧割当2007

    • Author(s)
      ウィシディスーリヤ ハシタ ムトゥマラ, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD2007-31

      Pages: 85-90

    • NAID

      110006291420

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] 超高速ステレオビジョンVLSIプロセッサの設計2007

    • Author(s)
      張山昌論, 横山直人, 吉田恒, 亀山充隆
    • Journal Title

      第13回画像センシングシンポジウム予稿集

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
  • [Journal Article] ユニバーサルな知能集積システムの構築を目指して2007

    • Author(s)
      亀山充隆
    • Journal Title

      多値論理研究ノート Vol.30,NO.10

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] データ圧縮に基づく画像処理VLSIアーキテクチャとその応用2007

    • Author(s)
      吉田 恒, 小林 康浩, 張山 昌論, 亀山 充隆
    • Journal Title

      電子情報通信学会技術研究報告 ICD2007-100

      Pages: 11-14

    • NAID

      110006453357

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
  • [Journal Article] 3次元情報を用いた車両検出アルゴリズムとそのVLSIアーキテクチャ2007

    • Author(s)
      山下 健策, 佐々木 明夫, 張山 昌論, 亀山 充隆
    • Journal Title

      電子情報通信学会技術研究報告 ICD2007-99

      Pages: 5-9

    • NAID

      110006453356

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
  • [Journal Article] 形状特徴を用いた人物抽出アルゴリズムとそのVLSIアーキテクチャ2007

    • Author(s)
      橋本翔太, 佐々木明夫, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会信学技報 Vol.107,No.382,ICD2007-13

      Pages: 77-82

    • NAID

      110006546968

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] 非同期ビットシリアルアーキテクチャに基づくフィールドプログラマブルVLSIの構成2007

    • Author(s)
      石原翔太, 張山昌論, 亀山充隆
    • Journal Title

      電気関係学会東北支部連合大会 2E18

      Pages: 192-192

    • NAID

      130005444444

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
  • [Journal Article] 操作系列特徴に基づく情報家電ユーザ支援用確率推論システム2007

    • Author(s)
      千頭和周平, 亀山充隆
    • Journal Title

      電気関係学会東北支部連合大会 1E08

      Pages: 165-165

    • NAID

      130005444408

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
  • [Journal Article] 細粒度アーキテクチャに基づくフィールドプログラマブルVLSIの開発2007

    • Author(s)
      張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会エレクトロニクスソサイエティ大会 C-12-11

      Pages: 66-66

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Annual Research Report 2007 Final Research Report Summary
  • [Journal Article] Design of a Multi-Context FPVLSI based on an AsynchronousBit-Serial Architecture2007

    • Author(s)
      Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
    • Journal Title

      Sixth IEEE Dallas Circuits and Systems Workshop

      Pages: 59-62

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] ウィンドウ演算のための最適スケジューリング・メモリアロケーション2007

    • Author(s)
      小林康浩, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会論文誌 Vo1. J90-D, No.5

      Pages: 1178-1193

    • NAID

      110007380712

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design of a Multi-Context FPVLSI based on an Asynchronous Bit-Serial Architecture2007

    • Author(s)
      Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka Kameyama
    • Journal Title

      Sixth IEEE Dallas Circuits and Systems Workshop

      Pages: 59-62

    • NAID

      120001182116

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] 相互結合網簡単化を考慮した遺伝的アルゴリズムに基づく電源・しきい値電圧割当2007

    • Author(s)
      ウィシディスーリヤハシタムトゥマラ, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD2007-31

      Pages: 85-90

    • NAID

      110006291420

    • Related Report
      2007 Annual Research Report
  • [Journal Article] ユニバーサルな知能集積システムの構築を目指して2007

    • Author(s)
      亀山充隆
    • Journal Title

      多値論理研究ノート Vo1. 30, No.10

    • Related Report
      2007 Annual Research Report
  • [Journal Article] 形状特徴を用いた人物抽出アルゴリズムとそのVLSIアーキテクチャ2007

    • Author(s)
      橋本翔太, 佐々木明夫, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会信学技報 Vol.107, No.38 2,ICD-2007-133

      Pages: 77-82

    • NAID

      110006546968

    • Related Report
      2007 Annual Research Report
  • [Journal Article] ウィンドウ並列・ピクセル並列アーキテクチャに基づくステレオビジョンプロセッサ2006

    • Author(s)
      横山直人, 張山昌論, 小林康浩, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD2005-212

      Pages: 43-46

    • NAID

      10017255609

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] 多値・二値ハイブリッドコンテクストスイッチング信号を用いたマルチコンテクストFPGAのアーキテクチャ2006

    • Author(s)
      中谷好博, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD2005-211

      Pages: 37-42

    • NAID

      10017255603

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006

    • Author(s)
      Masanori HARIYAMA, Shigeo YAMADERA, and Michitaka KAMEYAMA
    • Journal Title

      IEICE Trans. Electron. Vol. E89-C, No. 11

      Pages: 1551-1558

    • NAID

      110007538691

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Prospects of Intelligent Integrated Systems for Real-World Applications2006

    • Author(s)
      Michitaka Kameyama
    • Journal Title

      IEEE International Conference on Computers and Devices for Communication CD-ROM

    • NAID

      10007386690

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Optimal Periodical Memory Allocation for Logic-in-Memory Imag Processors2006

    • Author(s)
      Masanori Hariyama, Michitaka Kameyama, and Yasuhiro Kobayashi
    • Journal Title

      IEEE Computer Society Anual Symposium on VLSI

      Pages: 193-196

    • NAID

      120001182132

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Bayesian-Networks-Based Motion Estimation for a Highly-Safe Intelligent Vehicle2006

    • Author(s)
      Nguyen Van Dan and Michitaka Kameyama
    • Journal Title

      SICE-ICASE International Joint Conference

      Pages: 6023-6026

    • NAID

      120001182138

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006

    • Author(s)
      Sunggae Lee, Masanori Hariyama and Michitaka Kameyama
    • Journal Title

      SICE-ICCAS

      Pages: 1446-1450

    • NAID

      110004748907

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment2006

    • Author(s)
      Masanori Hariyama, Waidyasooriya Hasitha Muthumala, and Michitaka Kameyama
    • Journal Title

      Proc. Asian Solid-State Circuits Conference

      Pages: 155-158

    • NAID

      120001182114

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] 1000frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006

    • Author(s)
      Masanori Hariyama, Naoto Yokoyama and Michitaka Kameyama
    • Journal Title

      Proc. Asian Solid-State Circuits Conference

      Pages: 123-126

    • NAID

      120001182113

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006

    • Author(s)
      Waidyasooriya Hasitha Muthumala, Masanori Hariyama, andMichitaka, Kameyama
    • Journal Title

      IEEE Asia Pacific Conference on Circuits and Systems

      Pages: 1266-1269

    • NAID

      110006291420

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] 高安全自動車道路抽出のための動的再構成可能アーキテクチャ2006

    • Author(s)
      李承啓, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD2006-51

      Pages: 63-67

    • NAID

      110004748907

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2006 Annual Research Report
  • [Journal Article] 画像処理プロセッサのための最適メモリアロケーション2006

    • Author(s)
      張山昌論, 小林康浩, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD2006-57

      Pages: 95-100

    • NAID

      110004748913

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2006 Annual Research Report
  • [Journal Article] 最適スケジューリングに基づく3眼ステレオビジョンVLSIプロセッサの構成2006

    • Author(s)
      横山直人, 張山昌論, 亀山充隆
    • Journal Title

      電子情報通信学会技術報告 ICD-2006-153

      Pages: 55-60

    • NAID

      10018707021

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2006 Annual Research Report
  • [Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006

    • Author(s)
      Masanori HARIYAMA, Shigeo YAMADERA, and Michitaka KAMEYAMA
    • Journal Title

      IEICE Trans. Electron Vol. E89-C, No. 11

      Pages: 1551-1558

    • NAID

      110007538691

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Prospects of Intelligent Integrated Systems for Real-World Applications2006

    • Author(s)
      Michitaka Kameyama
    • Journal Title

      IEEE International Conference on Computers and Devices for Communication, CD-ROM (CD-ROM)

    • NAID

      10007386690

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Optimal Periodical Memory Allocation for Logic-in-memory imag Processors2006

    • Author(s)
      Masanori Hariyama, Michitaka kameyama, and yasuhiro Kobayashi
    • Journal Title

      IEEE Computer Society Anual Symposium on VLSI

      Pages: 193-198

    • NAID

      120001182132

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Bayesian-Networks-Based Motion Estimation for a Highly-Safe Intelligent Vehicle2006

    • Author(s)
      Nguyen Van Dan and Michitaka Kameyama
    • Journal Title

      SICE-ICASE international Joint Conference

      Pages: 6023-6026

    • NAID

      120001182138

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006

    • Author(s)
      Sunggae Lee, masanori Hariyama and Michitaka Kameyama
    • Journal Title

      SICE-ICCAS

      Pages: 1446-1450

    • NAID

      110004748907

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Dynamically Reconfigurable Gata Array Based on Fine-Grained Switch Elements and Its CAD Environment2006

    • Author(s)
      Masanori hariyama, Waidyasoority Hasitha muthumala, and Michitaka Kameyama
    • Journal Title

      Proc. Asian Solid-State Circuits conference

      Pages: 155-158

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] 1000frame/sec Stereo Mateching VLSI Processor with Adaptive Window-Size Control2006

    • Author(s)
      Masanori Hariyama, Nato Yokoyama and Michitaka Kameyama
    • Journal Title

      Proc. Asian Solid-State Circuits Conference

      Pages: 123-126

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006

    • Author(s)
      Waidyasooriya Hasitha Muthumala, Masanori Hariyama, and Michitaka, Kameyama
    • Journal Title

      IEEE Asia Pacific Conference on Circuits and Systems

      Pages: 1266-1269

    • NAID

      110006291420

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification2006

    • Author(s)
      MasanoriHARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA
    • Journal Title

      IEICE Trans. Electron. Vol.E89-C, No.11

      Pages: 1551-1558

    • NAID

      110007538691

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Prospects of Intelligent Integrated Systems for Real-World Applications2006

    • Author(s)
      Michitaka Kameyama
    • Journal Title

      IEEE International Conference on Computers and Devices for Communication (CD-ROM)

    • NAID

      10007386690

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors2006

    • Author(s)
      MasanoriHariyama, Michitaka Kameyama, Yasuhiro Kobayashi
    • Journal Title

      IEEE Computer Society Anual Symposium on VLSI

      Pages: 193-198

    • NAID

      120001182132

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Bayesian-Networks-Based Motion Estimation for a Highly-Safe Intelligent Vehicle2006

    • Author(s)
      Nguyen Van Dan, Michitaka Kameyama
    • Journal Title

      SICE-ICASE International Joint Conference

      Pages: 6023-6026

    • NAID

      120001182138

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Processor Architecture for Road Extraction Based on Projective Transformation2006

    • Author(s)
      Sunggae Lee, Masanori Hariyama, Michitaka Kameyama
    • Journal Title

      SICE-ICCAS

      Pages: 1446-1450

    • NAID

      110004748907

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment2006

    • Author(s)
      Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama
    • Journal Title

      Proc. Asian Solid-State Circuits Conference

      Pages: 155-158

    • NAID

      120001182114

    • Related Report
      2006 Annual Research Report
  • [Journal Article] 1000frame/sec Stereo Matching VLSI Processor with Adaptive Window-Size Control2006

    • Author(s)
      Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
    • Journal Title

      Proc. Asian Solid-State Circuits Conference

      Pages: 123-126

    • NAID

      120001182113

    • Related Report
      2006 Annual Research Report
  • [Journal Article] GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design2006

    • Author(s)
      Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka, Kameyama
    • Journal Title

      IEEE Asia Pacific Conference on Circuits and Systems

      Pages: 1266-1269

    • NAID

      110006291420

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages2005

    • Author(s)
      Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama
    • Journal Title

      IEEE Transaction on Computers Vol.54,No.6

      Pages: 642-650

    • NAID

      120001182139

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005

    • Author(s)
      Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama
    • Journal Title

      IEICE Trans. Inf. & Syst. Vol.E88-D,No.7

      Pages: 1486-1491

    • NAID

      110003214339

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] FPGAImplementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005

    • Author(s)
      Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, and Michitaka Kameyama
    • Journal Title

      IEICE Trans. Fundamentals Vol.E88-A,No.12

      Pages: 3516-3522

    • NAID

      110004019457

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005

    • Author(s)
      Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
    • Journal Title

      IEICE Trans. Fundamentals Vol.E88-A No.12,

      Pages: 3298-3305

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005

    • Author(s)
      Weisheng Chong, Sho Ogata, Masanori Hariyama and Michitaka Kameyama
    • Journal Title

      Proc. International Parallel and Distributed Processing Symposium CD-ROM

    • NAID

      110003318215

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005

    • Author(s)
      Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
    • Journal Title

      Proc. IEEE Computer Society Annual Conference on VLSI

      Pages: 46-50

    • NAID

      120001182131

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simpoification2005

    • Author(s)
      Masanori Hariyama, Shigeo Yamadera and Michitaka Kameyama
    • Journal Title

      Proc. 48th IEEE International Midwest Symposium on Circuits and Systems

      Pages: 1867-1870

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] DSP-Specific Field-Programmable VLSI and Its CAD Environment2005

    • Author(s)
      Masanori Hariyama, Sho Ogata, and Michitaka Kameyama
    • Journal Title

      Proc. 48th IEEE International Midwest Symposium on Circuits and Systems

      Pages: 651-654

    • NAID

      120001182135

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architectgure2005

    • Author(s)
      Masanori Hariyama, Yasuhiro Kobayashi, Naoto Yokoyama, and Michitaka Kameyama
    • Journal Title

      Proc. 48th IEEE International Midwest Symposlum on Circuits and Systems

      Pages: 1219-1222

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Intelligent Integrated Systems for Human-Oriented Information Society2005

    • Author(s)
      Michitaka Kameyama
    • Journal Title

      GSIS International Symposium on Information Sciences of New Era

      Pages: 77-103

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005

    • Author(s)
      Masanori Hariyama, Sho Ogata, and Michitaka Kameyama, Yasutoshi Morita
    • Journal Title

      IEEE Asian Solid-State Circuits Conference (A-SSCC)

      Pages: 421-424

    • NAID

      120001182112

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] Derivation of Performance Speciflcation of Intelligent Integrated Systems in Environment of Human-Computer Interaction2005

    • Author(s)
      Yuta Sakai and Michi taka Kameyama
    • Journal Title

      The IASTED International Conference on Human-Computer Interaction

      Pages: 161-166

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary
    • Peer Reviewed
  • [Journal Article] 高安全知能自動車用VLSIプロセッサの性能仕様の決定法2005

    • Author(s)
      坂井勇太, 亀山充隆
    • Journal Title

      第5回計測自動制御学会制御部門大会

      Pages: 1-4

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] 対応点探索と差分画像処理に基づく道路抽出アルゴリズム2005

    • Author(s)
      李承啓, 張山昌論, 亀山充隆
    • Journal Title

      電気関係学会東北支部連合大会 2G14

      Pages: 260-260

    • NAID

      130005443759

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] ウィンドウ並列・ピクセル並列スケジューリングに基づく高信頼ステレオマッチングVLSIのアーキテクチャ2005

    • Author(s)
      横山直人, 張山昌論, 亀山充隆
    • Journal Title

      電気関係学会東北支部連合大会 2I8

      Pages: 328-328

    • NAID

      130005443855

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] 機能パスゲートを用いたマルチコンテクストFPGA2005

    • Author(s)
      中谷好博, 張山昌論, 亀山充隆
    • Journal Title

      電気関係学会東北支部連合大会 2I9

      Pages: 329-329

    • NAID

      130005443858

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] 確率と物理モデルに基づく高安全知能自動車の軌道予測システム2005

    • Author(s)
      Nguyen Van Dan, 亀山充隆
    • Journal Title

      電気関係学会東北支部連合大会 2E26

      Pages: 197-197

    • NAID

      130005443740

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2007 Final Research Report Summary 2005 Annual Research Report
  • [Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors using Multiple Supply voltages2005

    • Author(s)
      Masanori Hariyama, Tetsuya Aoyama, and Michitaka Kameyama
    • Journal Title

      IEEE Transaction on Computers Vol. 54, No. 6

      Pages: 642-650

    • NAID

      120001182139

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005

    • Author(s)
      Masanori Hariyama, Haruka Sasaki, and Michitaka Kameyama
    • Journal Title

      ELCE Trans. Inf. & Syst Vol. E88-D, No. 7

      Pages: 1486-1491

    • NAID

      110003214339

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] FPGAImplementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005

    • Author(s)
      Masanori Hariyama, yasuhiroKobayashi, Haruka Sasaki, and Michitaka Kameyama
    • Journal Title

      IEICE Trans. Fundamentals Vol. E88-A, No. 12

      Pages: 3516-3522

    • NAID

      110004019457

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005

    • Author(s)
      Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
    • Journal Title

      IEICE Trans. Fundamentals Vol. E88-A No. 12

      Pages: 3298-3305

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005

    • Author(s)
      Weisheng Chong, Sho Ogata, masanori hariyama and Michitaka Kameyama
    • Journal Title

      Proc. International Parallel and Distributed Processing Symposium, CD-ROM (CD-ROM)

    • NAID

      110003318215

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005

    • Author(s)
      Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
    • Journal Title

      Proc. IEEE Computer Society Annual Conference on vlsi

      Pages: 46-50

    • NAID

      120001182131

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architectgure2005

    • Author(s)
      Masanori Hariyama, Yasuhiro Kobayashi, naoto Yokoyama, and Michitaka Kameyama
    • Journal Title

      Proc. 48th IEEE International Midwest Symposium on Circuits and Systems

      Pages: 1219-1222

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005

    • Author(s)
      Masanori Hariyama, Sho Ogata, and Michitaka Kameyama, yasutoshi Morita
    • Journal Title

      IEEE Asian Solid-State Circuits Conference(A-SSCC)

      Pages: 421-424

    • NAID

      120001182112

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Derivation of Performance Specification of Intelligen Integrated Systems in Environment of Human-Computer Interaction2005

    • Author(s)
      Yuta Sakai and Michitaka Kameyama
    • Journal Title

      The IASTED International Conference on Human-Computer Interaction

      Pages: 161-166

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2007 Final Research Report Summary
  • [Journal Article] Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages2005

    • Author(s)
      Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
    • Journal Title

      IEEE Transaction on Computers Vol.54, No.6

      Pages: 642-650

    • NAID

      120001182139

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access2005

    • Author(s)
      Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
    • Journal Title

      IEICE Trans.Inf.& Syst. Vol.E88-D, No.7

      Pages: 1486-1491

    • NAID

      110003214339

    • Related Report
      2005 Annual Research Report
  • [Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005

    • Author(s)
      Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama
    • Journal Title

      IEICE Trans.Fundamentals Vol.E88-A, No.12

      Pages: 3516-3522

    • NAID

      110004019457

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Low-Power Field-Programmalble VLSI Using Multiple Supply Voltages2005

    • Author(s)
      Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
    • Journal Title

      IEICE Trans.Fundamentals Vol.E88-A, No.12

      Pages: 3298-3305

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory2005

    • Author(s)
      Weisheng Chong, Sho Ogata, Masanori Haariyama, Michitaka Kameyama
    • Journal Title

      Proc.International Parallel and Distributed Processing Symposium

    • NAID

      110003318215

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Novel Switch Block Architecture Using Non-Volatile Functional Pass-gate for Multi-Context FPGAs2005

    • Author(s)
      Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
    • Journal Title

      Proc.IEEE Computer Society Annual Conference on VLSI

      Pages: 46-50

    • NAID

      120001182131

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Minimizing Energy Consumption of VLSI Processors Based on Dual-Supply-Voltage Assignment and Interconnection Simpoification2005

    • Author(s)
      Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
    • Journal Title

      Proc.48th IEEE International Midwest Symposium on Circuits and Systems

      Pages: 3201-3201

    • Related Report
      2005 Annual Research Report
  • [Journal Article] DSP-Specific Field-Programmable VLSI and Its CAD Environment2005

    • Author(s)
      Masanori Hariyama, Sho Ogata, Michitaka Kameyama
    • Journal Title

      Proc.48th IEEE International Midwest Symposium on Circuits and Systems

      Pages: 3199-3199

    • NAID

      120001182135

    • Related Report
      2005 Annual Research Report
  • [Journal Article] FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture2005

    • Author(s)
      Masanori Hariyama, Yasuhiro Kobayashi, Naoto Yokoyama, Michitaka Kameyama
    • Journal Title

      Proc.48th IEEE International Midwest Symposium on Circuits and Systems

      Pages: 3194-3194

    • NAID

      110004019457

    • Related Report
      2005 Annual Research Report
  • [Journal Article] "Intelligent Integrated Systems for Human-Oriented Information Society2005

    • Author(s)
      Michitaka Kameyama
    • Journal Title

      GSIS International Symposium on Information Sciences of New Era

      Pages: 77-103

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Design of Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate2005

    • Author(s)
      Masanori Hariyama, Sho Ogata, Michitaka Kameyama, Yasutoshi Morita
    • Journal Title

      IEEE Asian Solid-State Circuits Conference(A-SSCC)

      Pages: 421-424

    • NAID

      120001182112

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Derivation of Performance Specification of Intelligent Integrated Systems in Environment of Human-Computer Interaction2005

    • Author(s)
      Yuta Sakai, Michitaka Kameyama
    • Journal Title

      The IASTED International Conference on Human-Computer Interaction

      Pages: 161-166

    • Related Report
      2005 Annual Research Report

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Published: 2005-04-01   Modified: 2016-04-21  

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