| Project/Area Number |
17300015
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyoto University (2006-2007)
Toyohashi University of Technology (2005) |
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Principal Investigator |
NAKASHIMA Hiroshi Kyoto University, Academic Center for Computing and Media Studies, Professor (10243057)
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| Co-Investigator(Kenkyū-buntansha) |
TSUMURA Tomoaki Nagoya Institute of Technology, Graduate School of Engineering, Associate Professor (00335233)
NAKADA Takashi Nara Institute of Science and Technology, Graduate School of Information Science, Assistant Professor (00452524)
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| Project Period (FY) |
2005 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥15,050,000 (Direct Cost: ¥14,000,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2007: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2006: ¥7,400,000 (Direct Cost: ¥7,400,000)
Fiscal Year 2005: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Keywords | simulation engineering / computer systems / system-on-chip / high-performance computing / ハイパフォーマンスコンピューティング / シミュレータ / マイクロプロセッサ / 並列処理 |
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| Research Abstract |
The research has been pursued aiming at the parallelization and performance improvement of cycle accurate simulation (CAS) for advanced IT systems with microprocessors as their key components. The major achievements of the research are the following simulation techniques.
1. Our parallelized CAS is combined with an in-order execution simulator to produce approximated partial results of the parallel simulation. In order to avoid that this sequential in-order simulator became a bottleneck, we devised an acceleration technique to generate a simulator specific to each workload automatically. This technique achieves up to 34-fold performance improvement for instruction level simulation.
2. We devised a new parallel simulation method in which the process of a simulation is divided into intervals along with time axis so that the intervals me executed in parallel The problem arisen from the dependency between intervals is solved by speculatively executing each interval with approximated partial result of preceding intervals using in-order simulation. As a result, our parallel execution with an eight-node PC cluster achieves up to 5.8-fold speed-up.
3. To estimate the worst-case delay caused by interrupts, which is required in the design of real-time systems, we devised O (FN) algorithms to analyze the worst-case miss increments of caches and branch predictors for a workload with N instructions and F interrupts. Furthermore, we devised a O (Nlog N)algorithm to calculate the delay itself accurately using CAS, which can be accelerated by parallelization, up to 9-fold with an eight-node PC cluster.
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