| Project/Area Number |
17300021
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kumamoto University |
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Principal Investigator |
SUEYOSHI Toshinori Kumamoto University, Graduate School of Science and Thchnology, Professor (00117136)
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| Co-Investigator(Kenkyū-buntansha) |
KUGA Morihiro Kumamoto University, Graduate School of Science and Technology, Associate Professor (80243989)
柴村 英智 熊本大学, 工学部, 助手 (10264136)
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| Project Period (FY) |
2005 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥15,750,000 (Direct Cost: ¥15,300,000、Indirect Cost: ¥450,000)
Fiscal Year 2007: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2006: ¥5,000,000 (Direct Cost: ¥5,000,000)
Fiscal Year 2005: ¥8,800,000 (Direct Cost: ¥8,800,000)
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| Keywords | Reconfigurable System / Fine Grained Cell / System LSI / FPGA / Real Time OS |
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| Research Abstract |
The following research results are obtained in according to "Purpose of the research" and "Research plan".
1. The Research for Reconfigurable Logic IP
VGLC(Variable Grain Logic Cell)is proposed reconfigurable device architecture for reconfigurable system. It has novelty in the variable grain structure unified fine grain and coarse grain architecture. We evaluate VGLC architecture with same routing resource of FPGA compared with conventional FPGA using manually mapped arithmetic circuit. The evaluation result shows that layout area of VGLC is minimized compared with conventional FPGA cluster with transistor level optimization. Also the result shows that the AT product is also minimized about 66%.
2. The Research of RTOS Enhancement and Logic Virtualization for Dynamically Reconfigurable System
We develop the mechanisms of RTOS enhancement and logic virtualization for dynamically reconfigurable system. These mechanisms support to keep executing without stopping the processing of the entire system with the task schedule including the reconfiguration task. The evaluation results show that the reconfigurable system using the mechanism is high practicality and effectively, because the mechanisms support self-reconfiguration with embedded processor and transparent function execution via network environment.
3. The Research of Design Tools for Reconfigurable System
We research the design tools of reconfigurable system for partial-reconfiguration, which supports effective reconfiguration with extracted shared function in the application circuits. The evaluation result shows the reconfiguration time is reduced about 60% with the shared circuit's implementation of JPEG decoder and MPEG-2 decoder. Furthermore, the design method for automatic extraction of shared circuits is studied. The result shows that the LUTs are reduced about 4%, registers are reduced about 23% and logic blocks are reduced about 9% in certain target application.
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