System Integration of Beyond-Binary Computing
| Project/Area Number |
17300022
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Tohoku Institute of Technology |
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Principal Investigator |
HIGUCHI Tatsuo Tohoku Institute of Technology, Department of Engineering, Visiting Professor (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
AOKI Takafumi Tohoku University, Graduate School of Information Sciences, Professor (80241529)
HOMMA Naofumi Tohoku University, Graduate School of Information Sciences, Assistant Professor (00343062)
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| Project Period (FY) |
2005 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
|
| Budget Amount *help |
¥7,640,000 (Direct Cost: ¥7,100,000、Indirect Cost: ¥540,000)
Fiscal Year 2007: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2006: ¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 2005: ¥2,800,000 (Direct Cost: ¥2,800,000)
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| Keywords | Computer System / System on Chip / Micro- / nano- devices / Multiple-Valued Logic / Electric Desien Automation |
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| Research Abstract |
The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. In order to overcome the performance bottlenecks, this research project investigates system integration based on a novel computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project :
1. A hardware description language called ARITH was developed for describing hardware algorithms in VLSI systems. By using ARUM, we developed an advanced library containing high-performance arithmetic algorithms using both binary and non-binary number systems. As an application, we used the proposed library to develop a practical module generator supporting various multiplier structures. The generator is available from our website, and is widely used all over the world.
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2. A new high-level design method with ARITH was developed for designing high-performance beyond-binary arithmetic circuits. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. For the prototype design, we used voltage-mode and current-mode CMOS technologies for binary logic and multiple-valued logic, respectively. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. The capability of the proposed method was investigated through some arithmetic circuit designs.
3. A content-addressable memory circuits based on Single-Electron Transistors (SETs) was developed and evaluated for studying next-generation low-power LSI circuits. Also, a redox microarray for wire-free circuit integration using artificial catalyst devices was investigated experimentally. A prototype of redox microarray was demonstrated through an excitable reaction-diffusion dynamics, which was implemented by chemical reaction(e.g. B-Z reaction)waves. The visualization of the chemical waves was also investigated. Less
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Report
(4 results)
Research Products
(87 results)
