| Budget Amount *help |
¥16,100,000 (Direct Cost: ¥15,500,000、Indirect Cost: ¥600,000)
Fiscal Year 2007: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
Fiscal Year 2006: ¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 2005: ¥7,700,000 (Direct Cost: ¥7,700,000)
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| Research Abstract |
In future, video information gathering through a camera on a mobile terminals becomes popular because camera modules become cheap. Howeve4 raw data through cameras are generally low SNR, and, therein, requires a lot of processing before actual use. The research target in this project consists of processing amount reduction for raw data handling by use of multi-resolution processing and the processor architecture establishment, which can wale up to TOPS (Ira Operations Per Second) processing capabffity under low power dissipation, with programmable capability for realizing a variety of applications. For raw data handling, color enhancement and foreground separation algorithms are evaluated for processing amount reduction by using multi-resolution. The color image enhancement uses single color element of H in the HSI color system, and it also employs wavelet transform for further reduction to 113. Foreground separation, using fine-to-coarse processing on Walsh spectrum domain, becomes stable and reduces the processing amount to only 10% of the original one. Both algorithms employs pixel wise processing including many conditional jump instructions, pipeline control of processors are not suitable, because of many NOP operations after JUMP instructions. As a result, a super-parallel DSP approach which does not employ pipeline control in every element processor is established for this purpose. The newly employed segment buses works quite well in block wise spatial operations, and it has been shown that segment bus approach is better than Systolic approach in terms of full search motion compensation. In order to reduce chip : sire, the clock frequency employed is set to the highest one under non-pipeline control As a preliminary hardware evaluation, FPGA implementation has been carried out and a single FPGAcan hold 96 DSPs of mid 1980s, resulting 50K gate count equivalently. A 1000K gate system will reach 280GOPS.
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