Research on False Test Avoidance for LSI Yield Improvement
| Project/Area Number |
17500039
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
WEN Xiaoqing Kyushu Institute of Technology, Graduate School of Computer Science and Systems Engineering, Associate Professor, 情報工学研究科, 助教授 (20250897)
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| Co-Investigator(Kenkyū-buntansha) |
KAJIHARA Seiji Kyushu Institute of Technology, Faculty of Computer Science and Systems Engineering, Professor, 情報工学部, 教授 (80252592)
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| Project Period (FY) |
2005 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 2006: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2005: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Keywords | LSI Test / Scan Design / Low Power Test / IR Drop |
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| Research Abstract |
In VLSI testing, test input data often causes high switching activity, which results in IR-drop, and thus signal propagation delay. It has been shown that a 10% supply voltage drop may increase path delay by 15%. This delay increase often causes faulted test response to be loaded into flip-flops in capture mode. As a result, it is especially important to reduce test-induced switching activity in capture mode. This research was focused on solving the yield loss problem by reducing test-induced switching activity. The achievements of this research are as follows:
I. Basic Techniques
A technique for handling intermediate faulty voltages in a deep-submicron circuit has been proposed. In addition, a method for speeding up fault simulation by using both complied-code and event-driven techniques have been developed.
II. At-Speed Test Techniques
Faults existing between two synchronous clock domains need to be detected in order to improve test quality. We proposed a inter-clock-domain at-speed test controller, which can be used in both ATE-based external test and BIST.
III. X-Bit Identification Techniques
Several techniques for identifying don't care bits (X-bits) from a fully-specified test set without any fault coverage loss have been developed. In addition to fault coverage, the small-delay detection capability can also be preserved.
IV. X-Filling Technique
Several techniques for determining logic values for X-bits in test cubes so that the resulting test set has lower switching activity have been proposed. These techniques can reduce IR-drop for either a single-capture scheme or a double-capture scheme. In addition, switching activity at all cells (FFs and gates) can be targeted.
V. Low-Power Test Generation Techniques
In order to further reduce capture switching activity, we proposed an ATPG method for directly generating logic bites for the purpose of low test power. Anew concept, called capture-conflict (C-conflict), was introduced for this low-power test generation.
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Report
(3 results)
Research Products
(12 results)
