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A Hardware Evaluation System for an Interconnection Network Using Reconfigurable Devices

Research Project

Project/Area Number 17500051
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionOkayama University of Science

Principal Investigator

KOHATA Masaki  Okayama University of Science, Faculty of Engineering, Professor, 工学部, 教授 (60170297)

Co-Investigator(Kenkyū-buntansha) UEJIMA Akira  Okayama University of Science, Faculty of Engineering, Lecturer, 工学部, 講師 (30311781)
Project Period (FY) 2005 – 2006
Project Status Completed (Fiscal Year 2006)
Budget Amount *help
¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2006: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 2005: ¥2,300,000 (Direct Cost: ¥2,300,000)
KeywordsParallel Processing / Interconnection Network / FPGA / PC Cluster / ネットワーク
Research Abstract

In this research, we designed and developed a network card for PC clusters using field programmable gate arrays (FPGA), and realized a PC cluster system with this card. This network card is a 32-bit PCI bus card and consists of one FPGA, two RAMs, and four connectors. The PCI interface, four communication ports, and a five-port switch are implemented in one FPGA, and the network configuration can be changed by reconfiguring the FPGA. The communication rate is recorded in one of the two RAMs, and the timing of events, such as communication start/end, are recorded in another RAM.
We developed software, including a device driver for the network card, communication library, and visualization tools. The device driver is implemented as a kernel module for the Linux OS. The communication library provides basic communication functions, such as initialize, finalize, send, receive, broadcast, and barrier synchronization. In addition, a reconfiguration tool was developed, which reconfigures the FPGA in each PC of the cluster from a management PC.
We used the card to construct a PC cluster system connected by a ring network. For system evaluation, measurement and comparison of communication performance were performed while changing the depth of the communication buffer by reconfiguring the FPGA. The communication rate and timing were measured and visualized at the execution of Jacobi method, using the card's communication log function.
In conclusion, the test confirmed the basic system functions. We are currently expanding the system to a two-dimensional lattice-type network.

Report

(3 results)
  • 2006 Annual Research Report   Final Research Report Summary
  • 2005 Annual Research Report
  • Research Products

    (3 results)

All 2006

All Journal Article (3 results)

  • [Journal Article] FPGAによる並列計算機用ネットワークの実機評価システム2006

    • Author(s)
      上嶋明
    • Journal Title

      電子情報通信学会技術研究報告 Vol.1O6、No.199

      Pages: 55-60

    • NAID

      110004823479

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A Hardware Evaluation System for Interconnection Networks by Using an FPGA based Network Card2006

    • Author(s)
      Akira Uejima
    • Journal Title

      IEICE Technical Report Vol.106, No.199

      Pages: 55-60

    • NAID

      110004823479

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] FPGAによる並列計算機用ネットワークの実績評価システム2006

    • Author(s)
      上嶋明
    • Journal Title

      電子情報通信学会技術研究報告 Vol.106、No.199

      Pages: 55-60

    • Related Report
      2006 Annual Research Report

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Published: 2005-04-01   Modified: 2016-04-21  

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