Research on basic technologies for physical design of large scale system LSI

• Project/Area Number: 17560319
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Waseda University
• Principal Investigator: YOSHIMURA Takeshi Waseda University, 大学院・情報生産システム研究科, 教授 (80367177)
• Project Period (FY): 2005 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥3,410,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥510,000); Fiscal Year 2008: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2007: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000); Fiscal Year 2006: ¥600,000 (Direct Cost: ¥600,000); Fiscal Year 2005: ¥600,000 (Direct Cost: ¥600,000)
• Keywords: システムLSI / 物理設計 / 回路設計・CAD / アルゴリズム / 電子デバイス・集積回路

Research Abstract

大規模システムLSI物理設計基盤技術として,フロアプラン手法、超高速回路のクロックスキュー最適化手法,および、物理設計と連携した上流設計手法の研究を行なった。そして、フロアプランでは従来比で配線長を約20%、計算時間を70%~85%削減する手法を提案した。また、クロックスキュー最適化ではラグランジュ緩和法を、上流設計手法では最小コストフローを用いたスケジューリング手法を提案し、いずれも従来を上回る結果を得た。

Research Products

• [Journal Article] Exploration of Schedule Space by Random Walk (2009)
  • Author(s): Liangwei Ge, Song Chen and Takeshi Yoshimura
  • Journal Title: IPSJ Transactions on System LSI Design Methodologyv Vol.2 Pages: 0-0
  • NAID: 130000120663
  • Peer Reviewed
• [Journal Article] Exploration of Schedule Space by Random Walk (2009)
  • Author(s): Liangwei Ge, Song Chen, Takeshi Yos himura
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol. 2 Pages: 30-42
  • NAID: 130000120663
  • Peer Reviewed
• [Journal Article] Fixed-Outline Floorplanning: Block Position Enumeration and a New Method for Calculating Area Costs (2008)
  • Author(s): Song Chen and Takeshi Yoshimura
  • Journal Title: IEEE Transactions on CAD Vol.27/No.5 Pages: 858-871
  • Peer Reviewed
• [Journal Article] Nakamura and Takeshi Yoshimura, "A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition" (2008)
  • Author(s): Liangwei Ge, Song Chen
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol.1/No.1 Pages: 67-77
  • Peer Reviewed
• [Journal Article] A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition (2008)
  • Author(s): Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol. 1 Pages: 67-77
  • NAID: 130002073182
  • Peer Reviewed
• [Journal Article] Fixed-Outline Floorplanning : Block Position Enumeration and a New Method for Calculating Area Costs (2008)
  • Author(s): Song Chen, Takeshi Yoshimura
  • Journal Title: IEEE Transactions on CAD Vol. 27 Pages: 858-871
  • Peer Reviewed
• [Journal Article] Construction of an (r11,r12,r22)-Tournament from a Score Sequence Pair (2007)
  • Author(s): Masaya Takahashi, Takahiro Watanabe and Takeshi Yoshimura
  • Journal Title: Proceedings of International Symposium on Circuits and Systems (ISCAS 2007) Pages: 3403-3406
  • Peer Reviewed
• [Journal Article] (2007)
  • Author(s): Liangwei Ge, Song Chen, Takeshi Yoshimura, 他
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E90-A/9 Pages: 1940-1948
  • Peer Reviewed
• [Journal Article] A Fixed-Outline Floorplanning Method (2007)
  • Author(s): Takeshi Yosihmura and Song Chen
  • Journal Title: Proceedings of ASCON2007 Pages: 1070-1075
  • Peer Reviewed
• [Journal Article] Performance Maximized Interlayer Via Planning for 3D Ics (2007)
  • Author(s): Jun Lu, Song Chen, and Takeshi Yoshimura
  • Journal Title: Proceedings of ASICON2007 Pages: 1096-1099
  • Peer Reviewed
• [Journal Article] Score Sequence Pair Problems of(r11,r12,r22)-Tournaments〜Determination of Realizability (2007)
  • Author(s): Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
  • Journal Title: IEICE Transactions on Information and Systems Vol.E90-D,No.2 Pages: 440-448
• [Journal Article] A Stable Fixed-Outline Floorplanning Method (2007)
  • Author(s): Song Chen, Takeshi Yoshimura
  • Journal Title: Proceedings of International Symposium on Physical Design(ISPD2007)
• [Journal Article] Removal of Overlapped Freedom during Scheduling in High Level Synthesis (2006)
  • Author(s): Liangwei Ge, Kouhei Isoda, Takeshi Yoshimura
  • Journal Title: Proceedings of the 13th Workshop on Synthesis And System Intergration of MIxed Technologies
• [Journal Article] Domino Logic Synthesis System and Its Applications (2006)
  • Author(s): Ko Yoshikawa, Shigeto Inui, Yuichi Nakamura, Takeshi Yoshimura
  • Journal Title: Jouranal of Circuits, Systems and Computers Vol.15,No.3
• [Journal Article] A Consideration of the Score Sequence Problems of (R11,R12,R22)-Tournaments (2006)
  • Author(s): Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
  • Journal Title: Proceeding of abstract, International Mathematical Conference at Belgrade Pages: 50-51
• [Journal Article] On the Number of 3-D IC Floorplan COnfigurations and a Solution Perturbation Method with Good Convergence (2006)
  • Author(s): Song Chen, Takeshi Yoshimura
  • Journal Title: Proceedings of IEEE Asia Pacific Conference on Circuits and Systems at Singapore (Best Paper Award)
• [Journal Article] Realizability of Score Sequence Pair of an (r11,r12,r22)-Tournament (2006)
  • Author(s): Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
  • Journal Title: Proceedings of IEEE Asia Pacific Conference on Circuits and Systems at Singapore Pages: 1021-1024
• [Journal Article] Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs (2006)
  • Author(s): Yuichi Nakamura, Takeshi Yoshimura
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A,No.12 Pages: 3458-3463
  • NAID: 110007537848
• [Journal Article] Score Sequence Pair Problems of (r11,r12,r22)-Tournaments--Construction-- (2006)
  • Author(s): Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
  • Journal Title: IEICE CAS研究会資料
• [Journal Article] An Engineering Change Orders Design Method based on Patchwork-like Partitioning for High Performance LSIs (2005)
  • Author(s): Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura
  • Journal Title: IEICE Transactions Vol.E88-A, No.12 Pages: 3351-3357
  • NAID: 110004019436
• [Journal Article] Design and Implementation of an EOS Chip (2005)
  • Author(s): Liangwei ge, Takeshi Yoshimura
  • Journal Title: Proc.6-th International Conference on ASIC
• [Journal Article] A Fast Chip-Scale Power Estimation Method for Large and Complex LSIs Based on Hierarchical Analysis (2005)
  • Author(s): Yuichi Nakamura, T.Yoshimura
  • Journal Title: Proc.International Symposium on Circuits and Systems (ISCAS)
• [Journal Article] Solving the rectangular packing problem by a Combined Order-based GA/SA based on sequence-pair (2005)
  • Author(s): Wang Shen, Takeshi Yoshimura
  • Journal Title: Proc.of DA-Symposium
• [Journal Article] Max-Flow Scheduling in High Level Synthesis (2005)
  • Author(s): Liangwei Ge, Kouhei Isoda, Takeshi Yoshimura
  • Journal Title: IEICE CAS研究会資料
  • NAID: 110004020765
• [Presentation] Lagrangian relaxation based register placement for high-performance circuits (2009)
  • Author(s): M.-F. Chiang, T. Okamoto, and T. Yoshimura
  • Organizer: Proc. 10th International Symposium on Quality Electronic Design, San Jose, USA
  • Place of Presentation: USA
• [Presentation] A generalized v-shaped multi-level method for large scale Foorplanning (2009)
  • Author(s): S. Chen, Z. Xu, T. Yoshimura
  • Organizer: 10th International Symposium on Quality Electronic Design
  • Place of Presentation: San Jose, USA
• [Presentation] Lagrangian relaxation based register placement for high-performance circuits (2009)
  • Author(s): M. -F. Chiang, T. Okamoto, T. Yoshimura
  • Organizer: 10th International Symposium on Quality Electronic Design
  • Place of Presentation: San Jose, USA
• [Presentation] A synthesis method of general Floating-point arithmetic units by aligned partition (2008)
  • Author(s): L. Ge, S. Chen, Y. Nakamura, T. Yoshimura
  • Organizer: the 23rd International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Shimonoseki, Japan
  • Year and Date: 2008-07-07
• [Presentation] A Multilevel Fixed-outline Floorplanning for Large-scale IC Design (2008)
  • Author(s): Zheng Xu, Song Chen and Takeshi Yoshimura
  • Organizer: 電子情報通信学会2008年総合大会
  • Place of Presentation: 北九州学術研究都市
  • Year and Date: 2008-03-18
• [Presentation] Automatic implementation of arithmetic functions in high-level synthesis (2008)
  • Author(s): L. Ge, S. Chen, T. Yoshimura
  • Organizer: 9th International Conference on Solid-state and Integrated-Cirouit Technology
  • Place of Presentation: Beijing, China
• [Presentation] High-speed, pipelined implementation of squashing functions in neural networks (2008)
  • Author(s): L. Ge, S. Chen, T. Yoshimura
  • Organizer: 9th International Conference on Solid-state and Integrated-Cirouit Technology
  • Place of Presentation: Beijing, China
• [Presentation] A new implementation of multilevel framework for interoonnect-driven Foorplanning (2008)
  • Author(s): Z. Xu, S. Chen, T. Yoshimura, Y. Fang
  • Organizer: the 23rd International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Shimonoseki, Japan
• [Presentation] On objective functions for Fixed-outline Foorplanning (2008)
  • Author(s): L. Wang, X. Zhang, S. Chen, T. Yoshimura
  • Organizer: the 23rd International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Shimonoseki, Japan
• [Presentation] Exploration of schedule space by random walk (2008)
  • Author(s): L. Ge, S. Chen, T. Yoshimura
  • Organizer: the 23rd International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Shimonoseki, Japan
• [Presentation] Lagrangian relaxation based inter-layer signal via assignment for 3-d ICs (2008)
  • Author(s): S. Chen, Liangwei Ge, M. -F. Chiang, T. Yoshimura
  • Organizer: The 21st Workshop on Circuits and Systems in Karuizawa
  • Place of Presentation: Karuizawa, Japan
• [Presentation] Weighted Juniper insertion for antenna Fixing (2008)
  • Author(s): M. -F. Chiang, T. Yoshimura
  • Organizer: The 21st Workshop on Circuits and Systems in Karuizawa
  • Place of Presentation: Karuizawa, Japan
• [Presentation] Post-Lavout Redundant-Via lnsertion for Yield Enhancement (2007)
  • Author(s): Mei-Fang Chiang and Takeshi Yoshimura
  • Organizer: The 2nd International Ph.D.Student Workshop on SOC
  • Place of Presentation: 台湾大学
  • Year and Date: 2007-07-23
• [Presentation] On Objective Functons for Fixed-Outline Floorplanning (2007)
  • Author(s): Lu Wang, Xiaolin Zhang, Song Chen and Takeshi Yoshimura
  • Organizer: 電子情報通信学会2008年総合大会
  • Place of Presentation: 北九州学術研究都市
  • Year and Date: 2007-03-18
• [Presentation] A Stable Fixed-Outline Floorplanning Method (2007)
  • Author(s): N.Song Chen and Takeshi Yoshimura
  • Organizer: Proc. of International Symposium on Physical Design (ISPD 2007)
• [Presentation] On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence (2006)
  • Author(s): Song Chen and Takeshi Yoshimura
  • Organizer: Proc. of IEEE Asia Pacific Conference on Circuits and Systems at Singapore (Best Paper Award)
• [Remarks] 上記の学会発表論文(3)が国際会議"IEEE Asia Pacific Conference on Circuits and Systems"よりBest Paper Awardを受賞した。