| Project/Area Number |
17560363
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
System engineering
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| Research Institution | The Institute of Statistical Mathematics |
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Principal Investigator |
FUKASAWA Atsushi Institute of statistical Mathematics, Department of Statistical Modeling, Designated Visiting Professor, モデリング研究系・特任客員教授 (70292711)
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| Co-Investigator(Kenkyū-buntansha) |
TAKIZAWA Yumi Institute of statistical Mathematics, Department of Statistical Modeling, Associate Professor, モデリング研究系, 助教授 (90280528)
ISHIGURO Makio Institute of statistical Mathematics, Department of Statistical Modeling, Professor, モデリング研究系, 教授 (10000217)
MIYANAGA Yoshikazu Hokkaido University, Graduate school of Information Science and Technology, Professor, 大学院・情報科学研究科, 教授 (20166185)
柴田 直 東京大学, 大学院・新領域創成科学研究科, 教授 (00187402)
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| Project Period (FY) |
2005 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2006: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 2005: ¥1,800,000 (Direct Cost: ¥1,800,000)
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| Keywords | Radio Channel / Spreading gain / Eye pattern / Transmission data rate |
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| Research Abstract |
Enhancement of transmission data rate is rapid in demand on mobile data service. Expanding of radio band is not easily permitted in law. Multi-value modulation degrades the quality of communication, and multi-code scheme is used in spite of reduction of number of user channels.
In this study, adaptive data rate scheme is studied time and channel dependent valuation of data rate and contents by users.
The W-CDMA Scheme is taken as the basis of this scheme. The system is assumed to be design by Software Defined Radio (SDR) technology for adaptive control data rate. The data rates of 64, 128, 256, 512 kbit/s and 1.024 Mbit/s are taken for 5MHz radio bandwidth at 2GHz. Sufficient characteristic with easy control was confirmed practically with computer simulation and prototype hardware designed with are Field Program Gate Array (FPGA) with a MPU and PC.
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