| Budget Amount *help |
¥42,510,000 (Direct Cost: ¥32,700,000、Indirect Cost: ¥9,810,000)
Fiscal Year 2020: ¥10,140,000 (Direct Cost: ¥7,800,000、Indirect Cost: ¥2,340,000)
Fiscal Year 2019: ¥12,350,000 (Direct Cost: ¥9,500,000、Indirect Cost: ¥2,850,000)
Fiscal Year 2018: ¥11,700,000 (Direct Cost: ¥9,000,000、Indirect Cost: ¥2,700,000)
Fiscal Year 2017: ¥8,320,000 (Direct Cost: ¥6,400,000、Indirect Cost: ¥1,920,000)
|
|---|
| Outline of Final Research Achievements |
In this research project, we have developed a design technology for the Galois-field arithmetic data path, which is the basis of cryptographic and error correction LSIs. First, (1) a formal design method for high-order arithmetic data paths based on redundant Galois field representations, such as polynomial ring representation and redundant representation basis, was developed, and (2) a formal verification method based on computer algebra applicable to the circuit representation was developed. We have then applied the formal design and verification method to the cryptographic processor data path as its application. In particular, we have designed and verified efficient and/or tamper-resistant processor data paths for the ISO / IEC international standard ciphers. Furthermore, (4) we have developed an automatic synthesis / verification system for higher-order Galois-field arithmetic data paths.
|
