Design methods for high performance-highly reliable systems using auto-backup mechanisms
| Project/Area Number |
17H01709
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | The University of Tokyo |
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Principal Investigator |
Fujita Masahiro 東京大学, 大学院工学系研究科(工学部), 教授 (70323524)
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| Project Period (FY) |
2017-04-01 – 2020-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥14,040,000 (Direct Cost: ¥10,800,000、Indirect Cost: ¥3,240,000)
Fiscal Year 2019: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2018: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2017: ¥5,850,000 (Direct Cost: ¥4,500,000、Indirect Cost: ¥1,350,000)
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| Keywords | 高性能計算 / 計算高信頼化 / 不揮発性メモリ / 計算再利用 / デバッグ手法 / テスト手法 / 量子回路 / VLSI配線 / ニューラルネットワーク処理 / AIエッジ処理 / 自動バックアップ / パワーゲーティング / ハイパフォーマンス・コンピューティング / 低消費電力 |
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| Outline of Final Research Achievements |
By utilizing the circuit design technology that allows adding up to four non-volatile memory layers freely after creating an ordinary CMOS circuit and connecting them freely, we have developed new design methodologies for high-performance and highly reliable hardware systems. Through several examples, it is shown that it is possible to achieve high performance by enabling a large amount of computation in the vicinity of the data processing section and high reliability of processing through the insertion of checkpoints. Since it is non-volatile, it has the advantage of almost no increase in power consumption even when buffering various types of information. Furthermore, we also studied its use for (1) logic design debugging method in VLSI, (2) easy data routing in VLSI, and (3) testing method for quantum circuits, and demonstrated its usefulness by proposing novel methods.
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| Academic Significance and Societal Importance of the Research Achievements |
現在、ますます世の中の処理が自動化され、一方、処理すべきデータ量が膨大になっているため、ハードウェアを利用した情報処理技術の一段の高性能化と高信頼化が必須となっている。本研究では、通常のCMOS回路を作成した後、自由に不揮発性メモリ層を最大4層程度まで追加し両者を自由に接続できる回路設計技術を利用することで、同じチップ面積を利用しながら、ハードウェアシステムの高性能化と高信頼化を同時に実現可能であることが示された。さらに、(1)VLSIにおける論理設計デバッグ手法、(2)VLSIにおけるデータ配線の容易化、(3)量子回路のテスト手法に体しても有効活用できることを新規手法を提案することで示した。
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Report
(4 results)
Research Products
(12 results)
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[Journal Article] SAT-Based On-Track Bus Routing2021
Author(s)
He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang
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Journal Title
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume: 40(4)
Issue: 4
Pages: 735-747
DOI
Related Report
Peer Reviewed / Open Access / Int'l Joint Research
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