| Budget Amount *help |
¥18,590,000 (Direct Cost: ¥14,300,000、Indirect Cost: ¥4,290,000)
Fiscal Year 2020: ¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2019: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2018: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2017: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
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| Outline of Final Research Achievements |
Transactional memory (TM) has shown promise as a parallel programming paradigm that can achieve high performance with easy writing. However, its hardware implementations does not support multi-nodes, while its software implementations does not have sufficient performance.
In this research project, we have shown that the TM performance can be improved by improving the scheduling and contention access resolution methods of the TM, and have realized a prototype of a multi-node TM that incorporates these improvements. Although this prototype is still insufficient for practical use, it partially solves the problems of conventional TMs and shows the potential of TMs as a high-performance computing platform.
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