| Budget Amount *help |
¥13,130,000 (Direct Cost: ¥10,100,000、Indirect Cost: ¥3,030,000)
Fiscal Year 2020: ¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2019: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2018: ¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2017: ¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
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| Outline of Final Research Achievements |
Towards the full-scale IoT (Internet of Things) era, novel signal-integrity improvement technologies are required for the high-spped digital signal transmission. In order to meet the demand, we have proposed the segmental transmission line (STL) and shown its high performances already. On the other hand, the STL has disadvantages of interconnection density decrease and const increase due to its requirement for finer manufacturing technology. The goal of this project is to overcome the disadvantage of the STL and to propose the transmission line that can improve the signal integrity degradation adaptively. We have newly proposed the C-STL (Capacitor-STL) to achieve the goal and have shown its effectiveness by the C-STL prototype and its measurements.
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