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大規模集積回路における寿命予測・障害予防に向けたクロスレイヤ設計手法

Research Project

Project/Area Number 17J06952
Research Category

Grant-in-Aid for JSPS Fellows

Allocation TypeSingle-year Grants
Section国内
Research Field Electron device/Electronic equipment
Research InstitutionKyoto University

Principal Investigator

辺 松  京都大学, 情報学研究科, 特別研究員(DC1)

Project Period (FY) 2017-04-26 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥2,500,000 (Direct Cost: ¥2,500,000)
Fiscal Year 2019: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2018: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2017: ¥900,000 (Direct Cost: ¥900,000)
Keywordsハードウェアアクセラレータ / セキュリティ / 準同型暗号 / ハードウェアセキュリティ / 機械学習 / セキュア推論 / Approximate computing / 静的タイミング解析 / 半導体信頼性
Outline of Annual Research Achievements

本年度は、集積回路の劣化状況や寿命の推定を十分に安全な方式で行うフレームワークの検討を行った。
1. Learning with Errors (LWE)のハードウェア基盤創出
前年度で得られた知見により、Learning with Errors (LWE)暗号に基づく秘密計算方式を実現するために、ハードウェア基盤の構築が重要であることが分かり、本年度では、そのさらなる効率化を検討した。南京航空航天大学と共同研究を行い、2018年に本研究の一部として発表された近似計算手法を暗号システムに適用する研究(DWE: Decrypting Learning with Errors with Errors)を、より汎用的なField Programmable Gate Array (FPGA)デバイスの上で実装し、実際のセキュリティプロトコルでその実用性を確かめた結果を、システム設計のトップ会議であるInternational Symposium on Circuits and Systems (ISCAS)に採択された。また、今年度にLWEとRing LWE (RLWE)対し設計した乗算器アーキテクチャ設計自動化分野における最難関会議であるDesign Automation Conference (DAC)に発表し、その関連研究もWorkshop on Synthesis and System Integration of Mixed Information Technologies (SASHIMI)で発表した。

2. 小型センサによる寿命推定
上記の安全方式の結果を踏まえ、小型センサによる寿命推定の計算方式を考え、SASHIMIで発表した。発表したセンサアーキテクチャを用いれば、簡単な計算で高精度な寿命推定が可能であることを示した。

Research Progress Status

令和元年度が最終年度であるため、記入しない。

Strategy for Future Research Activity

令和元年度が最終年度であるため、記入しない。

Report

(3 results)
  • 2019 Annual Research Report
  • 2018 Annual Research Report
  • 2017 Annual Research Report
  • Research Products

    (15 results)

All 2020 2019 2018 2017 Other

All Int'l Joint Research (1 results) Journal Article (3 results) (of which Peer Reviewed: 3 results,  Open Access: 3 results) Presentation (11 results) (of which Int'l Joint Research: 11 results)

  • [Int'l Joint Research] 南京航空航天大学(中国)

    • Related Report
      2019 Annual Research Report
  • [Journal Article] Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption2019

    • Author(s)
      S. Bian, M. Hiromoto, and T. Sato
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E102.A Issue: 2 Pages: 430-439

    • DOI

      10.1587/transfun.E102.A.430

    • NAID

      130007587609

    • ISSN
      0916-8508, 1745-1337
    • Year and Date
      2019-02-01
    • Related Report
      2018 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Coin flipping PUF: A novel PUF with improved resistance against machine learning attacks2018

    • Author(s)
      Y. Tanaka, S. Bian, M. Hiromoto, and T. Sato
    • Journal Title

      IEEE Transactions on Circuits and Systems--II: Express Briefs (TCASII)

      Volume: 65 Issue: 5 Pages: 602-606

    • DOI

      10.1109/tcsii.2018.2821267

    • NAID

      120006463756

    • Related Report
      2018 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Identification and Application of Invariant Critical Paths under NBTI Degradation2017

    • Author(s)
      Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E100.A Issue: 12 Pages: 2797-2806

    • DOI

      10.1587/transfun.E100.A.2797

    • NAID

      130006236529

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2017 Annual Research Report
    • Peer Reviewed / Open Access
  • [Presentation] AxMM: Area and Power Efficient Approximate Modulo Multiplier for R-LWE Cryptosystem2020

    • Author(s)
      Dur E Shahwar Kundi, Song Bian, Ayesha Khalid, Chenghua Wang, Maire O'Neill, and Weiqiang Liu
    • Organizer
      Proc. of IEEE International Symposium on Circuits and Systems
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange2019

    • Author(s)
      Song Bian, Masayuki Hiromoto, Takashi Sato
    • Organizer
      Proc. of ACM/IEEE Design Automation Conference
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Estimation of NBTI-Induced Timing Degradation Considering Duty Ratio2019

    • Author(s)
      Kunihiro Oshima, Song Bian and Takashi Sato
    • Organizer
      Proc. The 22nd workshop on synthesis and system integration of mixed information technologies
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Improved Multiplier Architecture on ASIC for RLWE-based Key Exchange2019

    • Author(s)
      Tatsuki Ono, Song Bian and Takashi Sato
    • Organizer
      Proc. The 22nd workshop on synthesis and system integration of mixed information technologies
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Towards Practical Homomorphic Email Filtering: A Hardware-Accelerated Secure Naive Bayesian Filter2019

    • Author(s)
      Song Bian, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      Asia and South Pacific Design Automation Conference (ASP-DAC)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] DArL: Dynamic Parameter Adjustment for LWE-Based Secure Inference2019

    • Author(s)
      Song Bian, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      Design, Automation & Test in Europe (DATE)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] DWE: Decrypting Learning with Errors with Errors2018

    • Author(s)
      Song Bian, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      ACM/IEEE Design Automation Conference (DAC)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Efficient Exploration of Worst Case Workload and Timing Degradation Under NBTI2018

    • Author(s)
      Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      Asia and South Pacific Design Automation Conference (ASP-DAC)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Study on NBTI-Induced Delay Degradation Considering Stress Frequency Dependence2018

    • Author(s)
      Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      International Symposium on Quality Electronic Design (ISQED)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] DWE: Decrypting Learning with Errors with Errors2018

    • Author(s)
      Song Bian, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      Design Automation Conference (DAC)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations2017

    • Author(s)
      Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato
    • Organizer
      Design Automation Conference (DAC)
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research

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Published: 2017-05-25   Modified: 2024-03-26  

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