• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Study on decompositions of index generation functions.

Research Project

Project/Area Number 17K00086
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system
Research InstitutionMeiji University

Principal Investigator

Sasao Tsutomu  明治大学, 理工学部, 専任教授 (20112013)

Project Period (FY) 2017-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2019: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2017: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Keywords国際研究者交流 / 線形関数 / 関数分解 / ルータ / CAM(連想メモリ) / パターンマッチング / 書き換え可能回路 / 変数最小化 / 分類関数 / 不完全定義関数 / 国際研究者交流、米国 / CAM(連想メモリ) / モンテカルロ法 / インデックス生成関数 / CAM(連想メモリ) / 論理設計
Outline of Final Research Achievements

An index generation function can be decomposed into two index generation functions, by partitioning the set of the input variables into two. With this property, an arbitrary index generation function can be represented with only index generation functions, by iterative decompositions of the original index generation function. In this research, we developed an efficient decomposition algorithm, where the number of inputs n is up to 500. Also, during the research, we developed a very efficient linear decomposition method. We also published a book on index generation functions from the U.S.A..The concept of index generation functions was extended to ''classification functions''. They are useful for machine learning and data mining.

Academic Significance and Societal Importance of the Research Achievements

インデックス生成関数は、連想メモリ(CAM)の機能を数学的に表現したものである。インデックス生成関数の能率の良い実現法を開発することにより、CAMの応用回路の大きさや消費電力を大幅に削減できるようになる。例えば、インターネットのルータやパターンマッチング回路である。本回路は、通常のメモリと若干の論理回路から実現できる。インデックス生成関数は、代数的な手法で実現可能であり、大規模回路にも適用できる。また、この手法は、インデックス生成関数を拡張した分類関数にも適用可能である。分類関数は、機械学習yやデータマイニングにも応用できるため、電池で動く小型製品に組み込み可能である。

Report

(4 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • 2017 Research-status Report
  • Research Products

    (43 results)

All 2019 2018 2017 Other

All Int'l Joint Research (4 results) Journal Article (3 results) (of which Int'l Joint Research: 2 results,  Peer Reviewed: 3 results) Presentation (28 results) (of which Int'l Joint Research: 26 results,  Invited: 3 results) Book (3 results) Remarks (4 results) Patent(Industrial Property Rights) (1 results) (of which Overseas: 1 results)

  • [Int'l Joint Research] Naval Postgraduate School(米国)

    • Related Report
      2019 Annual Research Report
  • [Int'l Joint Research] Naval Postgraduate School(米国)

    • Related Report
      2018 Research-status Report
  • [Int'l Joint Research] Mathematical Institute of SASA(セルビア)

    • Related Report
      2018 Research-status Report
  • [Int'l Joint Research] Naval Postgraduate School(米国)

    • Related Report
      2017 Research-status Report
  • [Journal Article] A Method to Detect Bit Flips in a Soft-Error Resilient TCAM2017

    • Author(s)
      Syafalni Infall、Sasao Tsutomu、Wen Xiaoqing
    • Journal Title

      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

      Volume: 37-8 Issue: 6 Pages: 1-1

    • DOI

      10.1109/tcad.2017.2748019

    • Related Report
      2018 Research-status Report 2017 Research-status Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs2017

    • Author(s)
      SASAO Tsutomu
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E100.D Issue: 8 Pages: 1574-1582

    • DOI

      10.1587/transinf.2016LOP0001

    • NAID

      130005876098

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2017 Research-status Report
    • Peer Reviewed
  • [Journal Article] A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions2017

    • Author(s)
      Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E100.D Issue: 8 Pages: 1583-1591

    • DOI

      10.1587/transinf.2016LOP0013

    • NAID

      130005876136

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2017 Research-status Report
    • Peer Reviewed / Int'l Joint Research
  • [Presentation] Remarks on the design of first digital computer in Japan - Contributions of Yasuo Komamiya2019

    • Author(s)
      R.S. Stankovic, T. Sasao, J. T. Astola, and ,A. Yamada,
    • Organizer
      International Conference on Computer Aided Systems Theory(EUROCAST-2019)
    • Related Report
      2019 Annual Research Report 2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] On a minimization of variables to represent sparse multi-valued input decision functions2019

    • Author(s)
      T. Sasao
    • Organizer
      DATE-2019 Workshop
    • Related Report
      2019 Annual Research Report 2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] Logic minimizers for partially defined functions2019

    • Author(s)
      T. Sasao, K. Matsuura, K. Kai, and Y. Iguchi,
    • Organizer
      University Booth at Design, Automation and Test in Europe (DATE 2019)
    • Related Report
      2019 Annual Research Report 2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] On a minimization of variables to represent sparse multi-valued input decision functions2019

    • Author(s)
      T. Sasao
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2019)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Maximally asymmetric multiple-valued functions2019

    • Author(s)
      J. T. Butler and T. Sasao
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2019)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A dynamic programming based method for optimum linear decomposition of index generation functions2019

    • Author(s)
      S. Nagayama, T. Sasao and J. T. Butler,
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2019)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Realizing all index generation functions by the row-shift method2019

    • Author(s)
      J. T. Butler and T. Sasao
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2019)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Enumerative analysis of asymmetric functions,2019

    • Author(s)
      J. T. Butler and T. Sasao,
    • Organizer
      Reed-Muller Workshop (RM-2019)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Thirty six years of EXOR logic synthesis: Memoir2019

    • Author(s)
      T. Sasao
    • Organizer
      Reed-Muller Workshop (RM-2019)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] An improved bound on the number of variables to represent index generation functions using linear decompositions2019

    • Author(s)
      T. Sasao
    • Organizer
      International Workshop on Logic and Synthesis (IWLS-2019),
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] On irreducible index generation functions2019

    • Author(s)
      T. Sasao, K. Matsuura and Y. Iguchi,
    • Organizer
      International Workshop on Logic and Synthesis (IWLS-2019),
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] On a memory-based realization of sparse multiple-valued functions2018

    • Author(s)
      T. Sasao
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2018),
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] An exact method to enumerate decomposition charts for index generation functions2018

    • Author(s)
      J. T. Butler and T. Sasao
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2018),
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] An exact optimization method using ZDDs for linear decomposition of index generation function2018

    • Author(s)
      S. Nagayama, T. Sasao and J. Butler
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2018),
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] A High-speed low-power deep neural network on an FPGA based on the nested RNS: Applied to an object detector2018

    • Author(s)
      H. Nakahara and T. Sasao
    • Organizer
      International Symposium on Circuits and Systems (ISCAS-2018)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Analysis of cyclic row-shift decompositions for index generation functions2018

    • Author(s)
      J. T. Butler and T. Sasao
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information Technologies" (SASIMI 2018),
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Method to identify affine equivalence classes of logic functions2018

    • Author(s)
      T. Sasao, K. Matsuura and Y. Iguchi
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information Technologies" (SASIMI 2018),
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Netlist conversion from costumer logic interface format (CLIF) to Verilog for legacy circuits2018

    • Author(s)
      I. Syafalni, K. Wakasugi, Y. Tongxin, T. Sasao and X. Wen,
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information Technologies" (SASIMI 2018),
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] A logic synthesis for multiple-output linear circuits2018

    • Author(s)
      T. Sasao
    • Organizer
      International Workshop on Logic & Synthesis (IWLS-2018)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Bit-flip errors detection using random partial don't-care keys for a soft-error-tolerant TCAM2018

    • Author(s)
      I. Syafalni, T. Sasao, and X. Wen
    • Organizer
      International Workshop on Logic & Synthesis (IWLS-2018)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Analysis of cyclic row-shift decompositions for index generation functions2018

    • Author(s)
      J. T. Butler and T. Sasao
    • Organizer
      The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Method to identify affine equivalence classes of logic functions2018

    • Author(s)
      T. Sasao, K. Matsuura and Y. Iguchi
    • Organizer
      The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies
    • Related Report
      2017 Research-status Report
  • [Presentation] Netlist conversion from costumer logic interface format (CLIF) to Verilog for legacy circuits2018

    • Author(s)
      I. Syafalni, K. Wakasugi, Y. Tongxin, T. Sasao and X. Wen,
    • Organizer
      The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies
    • Related Report
      2017 Research-status Report
  • [Presentation] Index generation functions: Minimization methods2017

    • Author(s)
      T. Sasao,
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2017)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] A random forest using a multi-valued decision diagram2017

    • Author(s)
      H. Nakahara, A. Jinguji, S. Sato and T. Sasao,
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2017)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] An exact optimization algorithm for linear decomposition of index generation functions2017

    • Author(s)
      S. Nagayama, T. Sasao and J.T. Butler
    • Organizer
      International Symposium on Multiple-Valued Logic (ISMVL-2017)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] On affine equivalence of logic functions2017

    • Author(s)
      T. Sasao and M. Maeta
    • Organizer
      International Workshop on Logic and Synthesis
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] Probe location checker for IC physical verification2017

    • Author(s)
      I. Syafalni, K. Wakasugi, and T. Sasao,
    • Organizer
      2017 IEEE TENCON
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Book] Index Generation Functions2019

    • Author(s)
      Tsutomu Sasao
    • Total Pages
      165
    • Publisher
      Morgan and Glaypool
    • ISBN
      9781681736754
    • Related Report
      2019 Annual Research Report
  • [Book] Further Improvements in the Boolean Domain2018

    • Author(s)
      Jon T. Butler and T. Sasao,
    • Total Pages
      536
    • Publisher
      Cambridge Scholars Publishe
    • ISBN
      9781527503717
    • Related Report
      2017 Research-status Report
  • [Book] Advance of Logic Synthesis2017

    • Author(s)
      T. Sasao and J. T. Butler,
    • Total Pages
      232
    • Publisher
      Springer
    • ISBN
      9783319672946
    • Related Report
      2017 Research-status Report
  • [Remarks] Tsutomu Sasao

    • URL

      http://www.lsi-cad.com/sasao/index.html

    • Related Report
      2019 Annual Research Report
  • [Remarks] 笹尾勤

    • URL

      http://www.lsi-cad.com/sasao/index-j.html

    • Related Report
      2019 Annual Research Report
  • [Remarks] LSI-CAD.COM

    • URL

      http://www.lsi-cad.com

    • Related Report
      2018 Research-status Report
  • [Remarks] Welcome to LSI-CAD

    • URL

      http://www.lsi-cad.com

    • Related Report
      2017 Research-status Report
  • [Patent(Industrial Property Rights)] Content addressable memory, an index generator, and a registered information update method2018

    • Inventor(s)
      Tsutomu Sasao
    • Industrial Property Rights Holder
      明治大学
    • Industrial Property Rights Type
      特許
    • Filing Date
      2018
    • Acquisition Date
      2018
    • Related Report
      2017 Research-status Report
    • Overseas

URL: 

Published: 2017-04-28   Modified: 2021-02-19  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi