A research on high-precision low-power ADC by digital assist technique
| Project/Area Number |
17K06400
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo City University (2018-2021)
Tokyo University of Science (2017) |
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Principal Investigator |
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| Project Period (FY) |
2017-04-01 – 2022-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2019: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2018: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2017: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Keywords | アナログデジタル変換器 / 集積回路 / A/D変換器 / 高精度 / 高分解能 / デジタルアシスト / 半導体集積回路 / 高速 / 低電力 / 回路設計 / CMOS |
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| Outline of Final Research Achievements |
We researched on the digital assisted technique for a circuit design on high-precision low-power ADCs (Analog to Digital Converters). As the progress of solid-state integrated circuit miniaturization, the performance of analog circuit is degrading, on the other hand, more larger scale digital circuitry can be integrated on the same die. In this research, we depicted cyclic AD converter architecture, even if the gain of the amplifier is not precisely two, if precise gain of beta (1<beta<2) can be measured, the binary AD conversion value can be calculated using beta by digital signal procession circuitry in the same die. In order to increase conversion speed, lower bits can be converted by successive approximation (SAR) ADC. By trial production of this architecture using 65nm CMOS process, we proved that the high-precision of 11-to-12 bits effective number of bits, 250 kSample/sec. and low-power of 300 micro-W can be achieved by this digital assisted hybrid AD converter architecture.
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| Academic Significance and Societal Importance of the Research Achievements |
集積回路の微細化によりアナログ回路の性能は劣化し、一方デジタル回路は大規模集積化が可能になる。情報処理はデジタル化されて高度な信号処理ができる世界になっているが、現実の物理量はアナログであり、A/D変換器の高精度化、低電力化、高速化はますます要求される。アナログの性能劣化をデジタルで補う技術は今後ますます重要になってくると考えられる。その一つの方法を提案・特許化・試作評価して実証した意義は重要である。試作化したアイデアの他、科研費の期間に他のデジタルアシストアナログ技術をいくつか提案しており、今後の高性能集積回路技術の開発に役立つと確信している。
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Report
(6 results)
Research Products
(37 results)
