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Quality Improvement of Natural Data for Security by Controling Initial State

Research Project

Project/Area Number 17K06404
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionWaseda University

Principal Investigator

Shinohara Hirofumi  早稲田大学, 理工学術院(情報生産システム研究科・センター), 特任教授 (50531810)

Project Period (FY) 2017-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2019: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2017: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
KeywordsPUF / TRNG / 乱数 / ビットエラー率 / ハードウェアセキュリティ / ホットエレクトロン注入 / 電子デバイス・機器 / セキュア・ネットワーク / 暗号・認証等
Outline of Final Research Achievements

Quality improvement of natural random data for IoT security has been done in this research. In order to obtain random number stably from weak natural signals e.g. device mismatch or thermal noise in the basic latch circuits, an idea to control the initial state is applied. In PUF, which generate device specific numbers constantly, the initial point is guided away from the dividing ridge for the final binary state. While in TRNG, which generate unpredictable number every time, the initial state is adjusted on the dividing ridge.
PUF have achieved no bit error without ECC under worst voltage and temperature corner conditions and after aging by further introducing mismatch enhancement technique through hot carrier injection.
Combination of TRNG and high output rate post processing circuit has successfully generated a high quality random bit with a rate of one bit from 6 TRNG cells raw outputs.

Academic Significance and Societal Importance of the Research Achievements

PUFは、暗号鍵の安全を守ることから信頼の礎と呼ばれている。従来は強力ECCで安定化していたが、回路が複雑で消費エネルギーも大きく、リアルタイム性にも乏しかった。本成果はECC不要なので、省エネルギー高速で、IoT端末適用が期待される。近年はゲート絶縁膜破壊や不揮発メモリを用いてエラーゼロの報告はある。標準CMOSプロセスで破壊痕跡なくエラーゼロを示した功績は大きい。
ラッチTRNGのコア回路は小さいが、出力が偏るためにフィードバック制御や多数のセルを準備する必要があった。本研究ではフィードバック制御無しに6セルだけから高品質乱数を得ることを実証したので、一層の小型省エネルギーに貢献できる。

Report

(4 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • 2017 Research-status Report
  • Research Products

    (9 results)

All 2020 2019 2018

All Journal Article (1 results) (of which Peer Reviewed: 1 results) Presentation (8 results) (of which Int'l Joint Research: 5 results,  Invited: 2 results)

  • [Journal Article] A 373-F? 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and VSS Bias-Based Dark-Bit Detection2020

    • Author(s)
      Liu Kunyang、Min Yue、Yang Xuan、Sun Hanfeng、Shinohara Hirofumi
    • Journal Title

      IEEE Journal of Solid-State Circuits

      Volume: 5 Pages: 1719-1732

    • DOI

      10.1109/jssc.2019.2963002

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Presentation] A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in2020

    • Author(s)
      Kunyang Liu, Hongliang Pu and Hirofumi Shinohara
    • Organizer
      IEEE 2020 Custom Integrated Circuits Conf. (CICC)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] High-Throughput & Power Efficiency 8 Bits Von Neumann Post-Processing with Waiting Strategy for True Random Number Generators2019

    • Author(s)
      Ruilin Zhang and Hirofumi Shinohara
    • Organizer
      TJCAS 2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique2018

    • Author(s)
      Kunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun and Hirofumi Shinohara
    • Organizer
      IEEE 2018 A-SSCC, pp.161-164, Nov. 2018.
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] High-Throughput Von Neumann Post-Processing for Random Number Generator2018

    • Author(s)
      Ruilin Zhang, Sijia Chen, Chao Wan, Hirofumi Shinohara
    • Organizer
      IEEE, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), D3-1, April 2018.
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias2018

    • Author(s)
      Xuanhao Zhang, Xiang Chen, Hanfeng Sun and, Hirofumi Shinohara
    • Organizer
      IEICE Technical Report, HWS2018-38, pp. 333-336, July 2018
    • Related Report
      2018 Research-status Report
  • [Presentation] 情報セキュリティのためのランダム回路2018

    • Author(s)
      篠原尋史
    • Organizer
      信学技報、ICD2018-11, pp. 45-46, 2018年 4月
    • Related Report
      2018 Research-status Report
    • Invited
  • [Presentation] High-Throughput Von Neumann Post-Processing for Random Number Generator2018

    • Author(s)
      Ruilin Zhang
    • Organizer
      IEEE, International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research
  • [Presentation] 情報セキュリティのためのランダム回路2018

    • Author(s)
      篠原 尋史
    • Organizer
      電子情報通信学会、ICD研究会
    • Related Report
      2017 Research-status Report
    • Invited

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Published: 2017-04-28   Modified: 2021-02-19  

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