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High-level optimization of memory references for productive and efficient development of FPGA accelerators

Research Project

Project/Area Number 17K12658
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system
Research InstitutionToyohashi University of Technology (2018-2019)
Tokyo Institute of Technology (2017)

Principal Investigator

Sato Yukinori  豊橋技術科学大学, 工学(系)研究科(研究院), 准教授 (30452113)

Project Period (FY) 2017-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2018: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2017: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
KeywordsFPGAアクセラレータ / カスタムコンピューティング / 高位合成 / ハード・ソフト協調設計 / Polyhedral最適化 / 計算機システム / ハイパフォーマンス・コンピューティング
Outline of Final Research Achievements

Recently, application-specific custom acceleration using FPGA is becoming popular and attracting attention. In the development process of FPGA acceleration systems, utilizing locality of memory references based on software features within an application and hardware features inherent in the accelerator itself is a key for highly efficient processing. In this project, we developed high-level optimization technique that aims at productive and efficient development of FPGA accelerators customized for each application. Throughout this project, we showed that utilizing multiple levels of hierarchical memory can improve the gain of such high-level optimization for locality. Finally, we summed up the challenges in the process of code transformation for productive high-level optimization.

Academic Significance and Societal Importance of the Research Achievements

FPGAによるアプリケーション特化型のカスタムアクセラレーションは、金融工学、ビッグデータ解析、人工知能分野など多岐にわたる分野でCPUやGPUによる汎用的なアプローチと比べて消費エネルギ効率の面で大きな優位性があることが報告されており、産業界の実利用や社会実装も広がっている。一方で、アプリケーション開発における開発コスト、設計の抽象化に伴う性能効率の低下が課題となっていた。本研究では、これらの課題に対して新規の高位最適化手法を提案し学術の発展に寄与したほか、アプリケーション特化型処理技術の普及に向けた基盤技術の1つとして展開していくことを目指すことを通して社会への還元を試みている。

Report

(4 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Research-status Report
  • 2017 Research-status Report
  • Research Products

    (14 results)

All 2020 2019 2018 2017

All Journal Article (3 results) (of which Peer Reviewed: 2 results,  Open Access: 1 results) Presentation (11 results) (of which Int'l Joint Research: 5 results,  Invited: 3 results)

  • [Journal Article] FPGA/GPU/CPUが集積されたヘテロSoC環境におけるプログラミング2020

    • Author(s)
      佐藤健太, 佐藤幸紀
    • Journal Title

      情報処理学会第61回プログラミング・シンポジウム予稿集

      Volume: 61 Pages: 75-88

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] FPGA/CPU混載型SoCを用いたソフトウェア・ハードウェア協調システムの開発事例 ~ Ultra96を用いたJulia set explorerの実装 ~2019

    • Author(s)
      佐藤健太, 佐藤幸紀
    • Journal Title

      電子情報通信学会 信学技報 RECONF2019-13

      Volume: 119 Pages: 67-72

    • Related Report
      2019 Annual Research Report
  • [Journal Article] An Autotuning Framework for Scalable Execution of Tiled Code via Iterative Polyhedral Compilation2019

    • Author(s)
      Sato Yukinori、Yuki Tomoya、Endo Toshio
    • Journal Title

      ACM Transactions on Architecture and Code Optimization

      Volume: 15 Issue: 4 Pages: 1-23

    • DOI

      10.1145/3293449

    • Related Report
      2018 Research-status Report
    • Peer Reviewed / Open Access
  • [Presentation] ソフトウェア性能最適化技術の概要とドメイン特化型カスタムコンピュータへの展開2020

    • Author(s)
      佐藤幸紀
    • Organizer
      電子情報通信学会 北陸支部 2019 年度支部講演会, 能美市, 2020年3月6日
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] FPGA/GPU/CPUが集積されたヘテロSoC環境におけるプログラミング2020

    • Author(s)
      佐藤健太, 佐藤幸紀
    • Organizer
      情報処理学会第61回プログラミング・シンポジウム
    • Related Report
      2019 Annual Research Report
  • [Presentation] FPGA/CPU混載型SoCを用いたソフトウェア・ハードウェア協調システムの開発事例 ~ Ultra96を用いたJulia set explorerの実装 ~2019

    • Author(s)
      佐藤健太, 佐藤幸紀
    • Organizer
      電子情報通信学会リコンフィギャラブルシステム研究会, 東京工業大学, 2019年5月10日
    • Related Report
      2019 Annual Research Report
  • [Presentation] Designing an FPGA Accelerator with Optimization and Specialization for On-Board DRAM2019

    • Author(s)
      Kenta Sato, Yukinori Sato
    • Organizer
      Poster Session, IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 23)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Designing an FPGA Accelerator with Optimization and Specialization for On-Board DRAM.2019

    • Author(s)
      Kenta Sato and Yukinori Sato.
    • Organizer
      IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 22). April, 2019. 2 pages. (Poster Presentation)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] An Autotuning Framework for Scalable Execution of Tiled Code via Iterative Polyhedral Compilation.2019

    • Author(s)
      Yukinori Sato, Tomoya Yuki, and,Toshio Endo.
    • Organizer
      The HiPEAC 2019 conference, Spain, Valencia, January 21-23, 2019
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] Computer systems and performance engineering for upcoming AI applications.2018

    • Author(s)
      Yukinori Sato.
    • Organizer
      5th International Conference on Advance Informatics: Concepts, Theory and Applications (ICAICTA 2018). Krabi, Thailand. August 14 - 17, 2018.
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] MISD方式データフローカスタムパイプラインの高位最適化技術.2018

    • Author(s)
      佐藤幸紀
    • Organizer
      第10回メニーコア・アーキテクチャ研究会. 2018年9月24-25日
    • Related Report
      2018 Research-status Report
    • Invited
  • [Presentation] 動的バイナリ変換を用いた透過的コード最適化におけるタイルサイズ選択の評価2018

    • Author(s)
      佐藤幸紀
    • Organizer
      HotSPA2018, IEICE CPSY/DC, IPSJ-ARC合同研究会. 2018-ARC-231. 7 pages
    • Related Report
      2018 Research-status Report
  • [Presentation] FPGAアクセラレータにおけるデータ参照局所性の高位最適化2017

    • Author(s)
      佐藤幸紀
    • Organizer
      HotSPA2017, IEICE-RECONF/CPSY/DC/RIS、 IPSJ-ARC合同研究会
    • Related Report
      2017 Research-status Report
  • [Presentation] Engineering software performance of hardware accelerators using open source compilers and tools2017

    • Author(s)
      Yukinori Sato
    • Organizer
      Position talk at panel discussion, The 4th ACM SIGPLAN International Workshop on Software Engineering for Parallel Systems (SEPS 2017)
    • Related Report
      2017 Research-status Report
    • Int'l Joint Research

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Published: 2017-04-28   Modified: 2021-02-19  

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