Self-Convergence Mechanism of Transistor Characteristics Variability for 0.1V Operation

• Project/Area Number: 17K18866
• Research Category: Grant-in-Aid for Challenging Research (Exploratory)
• Allocation Type: Multi-year Fund
• Research Field: Electrical and electronic engineering and related fields
• Research Institution: The University of Tokyo
• Principal Investigator: Hiramoto Toshiro 東京大学, 生産技術研究所, 教授 (20192718)
• Project Period (FY): 2017-06-30 – 2019-03-31
• Project Status: Completed (Fiscal Year 2018)
• Budget Amount: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000); Fiscal Year 2018: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000); Fiscal Year 2017: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
• Keywords: MOSFET / 大規模集積回路 / 特性ばらつき / SRAM / 低電圧

Outline of Final Research Achievements

The objective of this study is to lower the operation voltage of very large scale integration (VLSI) for ultra-low energy operation. A self-convergence method of transistor characteristics variability in static random access memory (SRAM) by applying multiple stress voltage has been proposed. The experimental results showed that the minimum operation voltage of SRAM was lowered by the self-convergence mechanism.

Academic Significance and Societal Importance of the Research Achievements

大規模集積回路(VLSI)の課題の一つは消費電力の削減であり，そのほぼ唯一の方法は電源電圧の低減である．ところが，VLSIを構成する微細トランジスタの特性ばらつきのため電源電圧の低減は困難であった．本研究で提案した自己収束機構により，SRAMと呼ばれるメモリの電源電圧が下げられることが明らかとなった．本研究は将来のVLSIの低消費電力化に繋がる成果である．

Research Products

• [Journal Article] Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application (2018)
  • Author(s): Mizutani Tomoko、Takeuchi Kiyoshi、Saraya Takuya、Kobayashi Masaharu、Hiramoto Toshiro
  • Journal Title: Japanese Journal of Applied Physics Volume: 57 Issue: 4S Pages: 04FD08-04FD08
  • DOI: 10.7567/jjap.57.04fd08
  • Peer Reviewed
• [Presentation] Multiple Stress Technique for Post-Fabrication Cell Stability Self-Improvement of Bulk SRAM Cell Array (2018)
  • Author(s): T. Mizutani
  • Organizer: IEEE Silicon Nanoelectronics Workshop
  • Int'l Joint Research
• [Presentation] SRAMの安定性自己修復手法における複数回ストレス印加の効果 (2018)
  • Author(s): 水谷朋子
  • Organizer: 電子情報通信学会シリコン材料・デバイス研究会
• [Presentation] 複数回ストレスを利用した特性ばらつき自己修復手法のBulk SRAMセルへの応用 (2018)
  • Author(s): 水谷朋子
  • Organizer: 第79回応用物理学会秋季学術講演会
• [Presentation] 複数回ストレスを利用した特性ばらつき自己修復手法によるSRAMデータ保持電圧の最小化 (2018)
  • Author(s): 水谷朋子，竹内 潔，更屋拓哉，小林正治，平本俊郎
  • Organizer: 第65回応用物理学会春季学術講演会
• [Presentation] Lowering Minimum Operation Voltage (Vmin) in SRAM Array by Post-Fabrication Self-Improvement of Cell Stability by Multiple Stress Application (2017)
  • Author(s): Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi and Toshiro Hiramoto
  • Organizer: International Conference on Solid State Devices and Materials (SSDM)
  • Int'l Joint Research