Bit-write minimizing codes for non-volatile memories and their application to normally-off computing
| Project/Area Number |
17K19986
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| Research Category |
Grant-in-Aid for Challenging Research (Exploratory)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Information science, computer engineering, and related fields
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| Research Institution | Waseda University |
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Principal Investigator |
Togawa Nozomu 早稲田大学, 理工学術院, 教授 (30298161)
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| Project Period (FY) |
2017-06-30 – 2019-03-31
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| Project Status |
Completed (Fiscal Year 2018)
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| Budget Amount *help |
¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2018: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2017: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Keywords | 不揮発メモリ / 書込み削減符号 / 符号化 / ノーマリオフ計算 |
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| Outline of Final Research Achievements |
Non-volatile memories play an important role in normally-off computing. Non-volatile memories have almost the same operation speed as the normal memories and its cell contents remain even if they are switched-off. However, non-volatile memories sometimes consume 10 times or more energy in writing compared to normal memories and how to reduce the number of writing bits is one of the largest problems. In this research, we developed bit-write reducing and error-correcting codes for non-volatile memories based on effectively clustering error-correcting codes. Experimental evaluation results demonstrate that the proposed bit-write reducing and error-correcting codes can be effectively applied to various classes of application programs.
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| Academic Significance and Societal Importance of the Research Achievements |
不揮発メモリの活用には，いかに書込みビット数を削減するかが大きな焦点となっていた．加えて，メモリセルは誤りを起こすことがあり，書込み削減と誤り訂正とを両立することが実用上，大きな意味を持つ．本研究で提案した書込みビット数と誤り訂正を両立する符号は，理論的に誤り訂正能力を保持したままビット書込み数を抑えることを証明したと同時に，さまざまなアプリケーションプログラムに適用した結果，実際にビット書込み数の削減を確認している．しかも誤り訂正能力は，もとの符号のものと同一であることも理論的に示されている．これらは，不揮発メモリを用いたノーマリオフ計算の発展に大きな意味を持つものと考えられる．
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Report
(3 results)
Research Products
(8 results)
