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VLSI platform with intelligent environment adaptation technology and its application to highly reliable brain LSI systems

Research Project

Project/Area Number 17KK0001
Research Category

Fund for the Promotion of Joint International Research (Fostering Joint International Research)

Allocation TypeMulti-year Fund
Research Field Intensification of Artifact Systems
Research InstitutionTohoku University

Principal Investigator

NATSUI MASANORI  東北大学, 電気通信研究所, 准教授 (10402661)

Project Period (FY) 2017 – 2022
Project Status Completed (Fiscal Year 2022)
Budget Amount *help
¥13,260,000 (Direct Cost: ¥10,200,000、Indirect Cost: ¥3,060,000)
Keywords集積回路 / 不揮発素子 / IoT / 高信頼化 / 脳型LSI / 知的環境適応型LSI設計技術
Outline of Final Research Achievements

In this research, this researcher aimed to realize high-level processing in an extremely compact system configuration by implementing flexible and complex processing based on the principles of learning and memory, massively parallel, and autonomous distribution in the information processing process of the brain as hardware algorithms. Inspired by the brain's plasticity (environmental adaptability), the resercher promoted the realization of a new concept of intelligent environment-adaptive LSI platform technology that is not an extension of conventional ones. The effectiveness of the proposed technology was demonstrated through the design and evaluation of various circuits for IoT applications.

Academic Significance and Societal Importance of the Research Achievements

情報科学技術の一層の進展に伴い,VLSIが果たす役割がより人間の生活に密着したものになっていくことは想像に難くない.本研究によって得られた成果は,人間に与えられた役割をこなす単なる道具としてではなく,人間の脳において行われるようなより高次の情報処理を可能とする次世代VLSIの実現を促すものであるとともに,限界を迎えつつあると考えられてきたVLSI設計におけるパラダイムシフトを現実のものとし,VLSI設計技術を含む次世代の科学・産業技術の重要な礎となる成果であるといえる.

Report

(7 results)
  • 2022 Annual Research Report   Final Research Report ( PDF )
  • 2021 Research-status Report
  • 2020 Research-status Report
  • 2019 Research-status Report
  • 2018 Research-status Report
  • 2017 Research-status Report
  • Research Products

    (44 results)

All 2023 2022 2021 2020 2019 2018

All Int'l Joint Research (1 results) Journal Article (8 results) (of which Peer Reviewed: 8 results,  Open Access: 2 results) Presentation (35 results) (of which Int'l Joint Research: 17 results,  Invited: 7 results)

  • [Int'l Joint Research] University of Toronto(カナダ)2018

    • Year and Date
      2018-03-23
    • Related Report
      2022 Annual Research Report
  • [Journal Article] Design of a Nonvolatile-Register-Embedded RISC-V CPU with Software-Controlled Data-Retention and Hardware-Acceleration Functions2023

    • Author(s)
      M. Natsui, K. Sakamoto, and T. Hanyu
    • Journal Title

      Memories - Materials, Devices, Circuits and Systems

      Volume: 4 Pages: 100035-100035

    • DOI

      10.1016/j.memori.2023.100035

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits2022

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 61

    • DOI

      10.35848/1347-4065/ac461a

    • Related Report
      2022 Annual Research Report 2021 Research-status Report
    • Peer Reviewed / Open Access
  • [Journal Article] 不揮発記憶機能が拓く新概念ロジックLSI設計技術とその将来展望2021

    • Author(s)
      夏井雅典, 羽生貴弘
    • Journal Title

      電子情報通信学会論文誌C

      Volume: J104-C Pages: 185-192

    • Related Report
      2021 Research-status Report
    • Peer Reviewed
  • [Journal Article] Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability2021

    • Author(s)
      M. Natsui, G. Yamagishi, and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 60 Issue: SB Pages: SBBB02-SBBB02

    • DOI

      10.35848/1347-4065/abdcb0

    • Related Report
      2020 Research-status Report
    • Peer Reviewed
  • [Journal Article] Impact of MTJ-Based Nonvolatile Circuit Techniques for Energy-Efficient Binary Neural Network Hardware2020

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 59 Issue: 5 Pages: 050602-050602

    • DOI

      10.35848/1347-4065/ab82ae

    • Related Report
      2020 Research-status Report
    • Peer Reviewed
  • [Journal Article] A 47.14μW 200MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
    • Journal Title

      IEEE Journal of Solid State Circuits

      Volume: 54 Issue: 11 Pages: 2991-3004

    • DOI

      10.1109/jssc.2019.2930910

    • Related Report
      2019 Research-status Report
    • Peer Reviewed
  • [Journal Article] Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware2019

    • Author(s)
      Natsui Masanori、Chiba Tomoki、Hanyu Takahiro
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 58 Issue: SB Pages: SBBB01-SBBB01

    • DOI

      10.7567/1347-4065/aafb4d

    • NAID

      210000135331

    • Related Report
      2018 Research-status Report
    • Peer Reviewed
  • [Journal Article] Design of MTJ-Based nonvolatile logic gates for quantized neural networks2018

    • Author(s)
      Natsui Masanori、Chiba Tomoki、Hanyu Takahiro
    • Journal Title

      Microelectronics Journal

      Volume: 82 Pages: 13-21

    • DOI

      10.1016/j.mejo.2018.10.005

    • Related Report
      2018 Research-status Report
    • Peer Reviewed
  • [Presentation] 不揮発ロジックLSI技術に基づく次世代エッジコンピューティングパラダイムの展望2023

    • Author(s)
      夏井雅典
    • Organizer
      NV-FPGA Initiative 第4回公開シンポジウム
    • Related Report
      2022 Annual Research Report
    • Invited
  • [Presentation] Prospects of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic2022

    • Author(s)
      M. Natsui, D. Suzuki, Y. Takako, A. Tamakoshi, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Design of a Low-Power FPGA-Based CNN Accelerator Based on Nonvolatile Logic-in-Memory Circuitry2022

    • Author(s)
      D. Suzuki, M. Natsui, A. Tamakoshi, Y. Takako, and T. Hanyu
    • Organizer
      2022 International Symposium on Nonlinear Theory and Its Applications (NOLTA2022)
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator2022

    • Author(s)
      K. Sakamoto, M. Natsui, and T. Hanyu
    • Organizer
      2022 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2022)
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Operation-Condition-Aware Dynamic Power Gating for Nonvolatile LSIs,2022

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      31st International Workshop on Post-Binary ULSI Systems
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] MTJベース量子化ニューラルネットワークハードウェアの書込みエネルギー削減手法に関する研究2022

    • Author(s)
      浅野健,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Related Report
      2022 Annual Research Report
  • [Presentation] 書込みエラー特性に基づく MTJ ベース不揮発レジスタの制御部最適化に関する一検討2022

    • Author(s)
      酒井楓,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Related Report
      2022 Annual Research Report
  • [Presentation] ビットエラー耐性を活用した省エネルギーニューラルネットワークの構成に関する基礎的研究2022

    • Author(s)
      浅野健,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合大会
    • Related Report
      2022 Annual Research Report
  • [Presentation] 書込みエラー検出機能を有する高信頼不揮発レジスタの構成2022

    • Author(s)
      酒井楓,夏井雅典,羽生貴弘
    • Organizer
      2022年度電気関係学会東北支部連合大会
    • Related Report
      2022 Annual Research Report
  • [Presentation] アクセラレータ制御命令を組み込んだRISC-Vベース省エネルギー不揮発CPUの構成2022

    • Author(s)
      坂本佳介,夏井雅典,羽生貴弘
    • Organizer
      LSIとシステムのワークショップ2022
    • Related Report
      2022 Annual Research Report
  • [Presentation] 不揮発LSI向け可変パワーゲーティングスイッチ構造とその動的制御に関する研究2022

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      ICD学生・若手研究会
    • Related Report
      2021 Research-status Report
  • [Presentation] Dynamic Power-Gating-Switch Control Technique and Its Application to an Energy-Efficient Embedded STT-MRAM2021

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      2021 International Conference on Solid State Devices and Materials (SSDM2021)
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] K.C.Smith賞受賞時の研究とその後の研究の展望について ~不揮発ロジックインメモリ構造を活用したポストプロセスばらつき補正技術とその応用展開~2021

    • Author(s)
      夏井雅典
    • Organizer
      第44回多値論理フォーラム
    • Related Report
      2021 Research-status Report
    • Invited
  • [Presentation] 磁気トンネル接合素子を活用した高性能・省エネルギー不揮発LSIの開発2021

    • Author(s)
      夏井雅典
    • Organizer
      R025先進薄膜界面機能創成委員会 第6回研究会
    • Related Report
      2021 Research-status Report
    • Invited
  • [Presentation] 次世代エッジコンピューティングを支える集積回路技術2021

    • Author(s)
      夏井雅典
    • Organizer
      電子情報通信学会東北支部学術講演会
    • Related Report
      2021 Research-status Report
    • Invited
  • [Presentation] 動作環境適応型パワーゲーティングスイッチ制御技術とその不揮発ロジックLSIへの応用2021

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2021 -VLSI設計の新しい大地-
    • Related Report
      2021 Research-status Report
  • [Presentation] Power-Gating Switch-Control Technique for Nonvolatile Logic LSI2021

    • Author(s)
      F. Zhong, M. Natsui, and T. Hanyu
    • Organizer
      The 4th Symposium for The Core Research Clusters for Materials Science and Spintronics
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Presentation] Design of a Magnetic-Tunnel-Junction-Based Nonvolatile Flip-Flop with Common-Mode Write Error Detection2020

    • Author(s)
      G. Yamagishi, M. Natsui, and T. Hanyu
    • Organizer
      2020 International Conference on Solid State Devices and Materials
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Presentation] 不揮発ロジックLSIのパワーゲーティングスイッチ制御技術に関する一検討2020

    • Author(s)
      鐘方岑,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2020 -VLSI設計の新しい大地-
    • Related Report
      2020 Research-status Report
  • [Presentation] Impact of nonvolatile-logic design techniques for spintronics-based edge AI computing2020

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      The 8th RIEC International Symposium on Brain Functions and Brain Computer
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] Design of a Resilient Nonvolatile Flip-Flop with Common-Mode Write Error Detection2020

    • Author(s)
      G. Yamagishi, M. Natsui, and T. Hanyu
    • Organizer
      The 3rd Symposium for The Core Research Clusters for Materials Science and Spintronics
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks2019

    • Author(s)
      T. Chiba, M. Natsui and T. Hanyu
    • Organizer
      49th IEEE International Symposium on Multiple-Valued Logic (ISMVL2019)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] Design of an MTJ-Based Fully-Nonvolatile Microcontroller LSI and Its Impact on IoT Applications2019

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      28th International Workshop on Post-Binary ULSI Systems
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] Nonvolatile Logic LSI Design Technology and Its Application to AI Hardware2019

    • Author(s)
      M. Natsui
    • Organizer
      2019 International Conference on Solid State Devices and Materials (SSDM2019)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal-Resistance Sensing Mechanism for Ternary Neural Network Hardware2019

    • Author(s)
      M. Natsui and T. Hanyu
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] 非相補抵抗状態検出機能を有する高信頼MTJベース不揮発性フリップフロップの構成2019

    • Author(s)
      山岸源征,夏井雅典,羽生貴弘
    • Organizer
      令和元年度電気関係学会東北支部連合大会
    • Related Report
      2019 Research-status Report
  • [Presentation] 省エネルギー二値化ニューラルネットワーク向けMTJベース積和演算回路の構成2019

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      デザインガイア2019 -VLSI設計の新しい大地-
    • Related Report
      2019 Research-status Report
  • [Presentation] Impact of MTJ-Based Nonvolatile Microcontroller LSI for IoT Applications2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, H. Sato, S. Ikeda, T. Endoh, and T. Hanyu
    • Organizer
      5th CIES Technology Forum / DAY 1 International Symposium
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research / Invited
  • [Presentation] MTJ-Based Nonvolatile Logic Gates for Quantized Neural Network Hardware2019

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      The 6th International Symposium on Brainware LSI
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu
    • Organizer
      2019 IEEE International Solid-State Circuits Conference (ISSCC2019)
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJHybrid Technology Achieving 47.14μW Operation at 200MHz2019

    • Author(s)
      M. Natsui
    • Organizer
      IEEE SSCS Kansai Chapter Technical Seminar
    • Related Report
      2018 Research-status Report
    • Invited
  • [Presentation] MTJベースばらつき補正機能を用いた2値化ニューラルネットワーク向け低消費電力・省面積bitcount回路の構成2019

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      第32回多値論理とその応用研究会
    • Related Report
      2018 Research-status Report
  • [Presentation] MTJ-Based Nonvolatile Ternary Logic Gate for Quantized Convolutional Neural Networks2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] MTJ-Based Nonvolatile Logic Gate for Binarized Convolutional Neural Networks and Its Impact2018

    • Author(s)
      M. Natsui, T. Chiba and T. Hanyu
    • Organizer
      2018 International Conference on Solid State Devices and Materials (SSDM2018)
    • Related Report
      2018 Research-status Report
  • [Presentation] 不揮発量子化ニューラルネットワーク構造に基づく小型・超低消費電力XNOR回路の構成2018

    • Author(s)
      千葉智貴,夏井雅典,羽生貴弘
    • Organizer
      平成30年度電気関係学会東北支部連合大会
    • Related Report
      2018 Research-status Report

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Published: 2018-01-25   Modified: 2025-01-30  

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