| Project/Area Number |
18063009
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Review Section |
Science and Engineering
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
IWAI Hiroshi Tokyo Institute of Technology, フロンティア研究センター, 教授 (40313358)
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| Co-Investigator(Kenkyū-buntansha) |
HATTORI Takeo 東京工業大学, フロンティア研究センター, 客員教授 (10061516)
TSUTSUI Kazuo 東京工業大学, 大学院・総合理工学研究科, 教授 (60188589)
KAKUSHIMA Kuniyuki 東京工業大学, 大学院・総合理工学研究科, 助教 (50401568)
PARHAT Ahmet 東京工業大学, フロンティア研究センター, 特任准教授 (00418675)
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| Project Period (FY) |
2006 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥43,600,000 (Direct Cost: ¥43,600,000)
Fiscal Year 2009: ¥10,400,000 (Direct Cost: ¥10,400,000)
Fiscal Year 2008: ¥10,400,000 (Direct Cost: ¥10,400,000)
Fiscal Year 2007: ¥11,400,000 (Direct Cost: ¥11,400,000)
Fiscal Year 2006: ¥11,400,000 (Direct Cost: ¥11,400,000)
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| Keywords | ばらつき / ゆらぎ / CMOS / ダブルゲート / FinFET / シリサイド / 感度解析 / トランジスタ / 3次元構造 / ロバストネス / 特性ばらつき / ショットキー / オン電流 / MOSFET / 3次元 / ショットキー接合 / 数値解析 / 三次元構造MOSFET / しきい値 / Schottky source / drain / エネルギー障壁 / 短チャネル効果 / Niシリサイド |
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| Research Abstract |
For the future large scale integrated circuit, new transistor with three-dimensional structures will be used in near future. However, variability of transistor characteristics, which is very significant problem on scaling down of device sizes, on the new type transistor has not been known well. In this work, comprehensive study of variability resulted from fluctuations of various device parameters was carried out, and proposed guiding principles for realizing robust transistors for the variability. In addition, a new process technology of silicide electrodes which will be useful to the robust transistors was developed.
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