| Project/Area Number |
18080005
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Review Section |
Science and Engineering
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| Research Institution | Yokohama National University |
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Principal Investigator |
YOSHIKAWA Nobuyuki Yokohama National University, 大学院・工学研究院, 教授 (70202398)
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| Co-Investigator(Kenkyū-buntansha) |
KANEDA Hisayoshi 国立大学法人横浜国立大学, 大学院・工学研究院, 助手 (30242382)
藤巻 朗 国立大学法人名古屋大学, 大学院工学研究科, 教授 (20183931)
中島 康治 国立大学法人東北大学, 電気通信研究所, 教授 (60125622)
明連 広昭 国立大学法人埼玉大学, 工学部, 助教授 (20219827)
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| Project Period (FY) |
2006 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥54,300,000 (Direct Cost: ¥54,300,000)
Fiscal Year 2009: ¥5,600,000 (Direct Cost: ¥5,600,000)
Fiscal Year 2008: ¥15,600,000 (Direct Cost: ¥15,600,000)
Fiscal Year 2007: ¥18,300,000 (Direct Cost: ¥18,300,000)
Fiscal Year 2006: ¥14,800,000 (Direct Cost: ¥14,800,000)
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| Keywords | 局在電磁波 / 単一磁束量子 / SFQ / 単一磁束量子回路 / 超伝導回路 / 低消費電力 / 信号処理回路 / FFT / 単一磁束量子論理回路 / サブテラヘルツ集積回路 / NbN接合 / MgB2接合 |
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| Research Abstract |
Single-flux-quantum (SFQ) integrated circuits, which combine SFQ circuits with loss-less superconducting passive transmission lines (PTLs), have extremely high-speed and low-power abilities. In this study, a technique to connect SFQ logic gates directly with PTLs was studied and a new cell library was developed. It was demonstrated that the junction number and power consumption of SFQ circuits were considerably reduced with this technique. FFT signal processors were also developed based on this technique for their digital-signal-processor application, and their high-speed operation was demonstrated.
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