| Budget Amount *help |
¥41,080,000 (Direct Cost: ¥31,600,000、Indirect Cost: ¥9,480,000)
Fiscal Year 2007: ¥16,120,000 (Direct Cost: ¥12,400,000、Indirect Cost: ¥3,720,000)
Fiscal Year 2006: ¥24,960,000 (Direct Cost: ¥19,200,000、Indirect Cost: ¥5,760,000)
|
|---|
| Research Abstract |
Objective of this program is to prove that the group III nitride is one of the most suitable materials for the fabrication of high power FET in the next generation. In FY2006, 1. Reduction of on resistance and improvement of the mutual conductance by surface passivation, 2. Small sub-threshold swing and low power loss in inverter circuit, 3. Controllability of the threshold voltage by changing barrier composition and thickness, and 4. Difference of the mobility underneath the gate-source and the gate were clarified. In order to realize high power devices, AN substrate is very promising because of the small lattice mismatch and the extremely high resistance. Therefore, in this program, 5. Growth of AIN substrate by sublimation on the 6H-SiC substrate, and 6. Growth of high quality AIN template on a sapphire substrate by high temperature MOVPE was conducted. Several papers were published for this issue.
In FY2007, relationship between thickness of SiN passivation film and the maximum drain current was found. By optimizing the SIN thickness to be 5 nm, the following performance can be successfully observed in the normally off JHFET; Maximum drain current density: 1.58×10^<-1> [A/mm], leakage current: 1.45×10^<-8> [A/mm], on/off ratio: higher than 7 orders of magnitude, sub-threshold swing: 90 [mV/dec.], on resistance: 3.4 [mΩcm^2]. In addition, breakdown voltage was as high as 325 V, which is sufficient for inverter circuits for small size air conditioner.
|
