A study of the integrated EDA tools for reconfigurable logic

• Project/Area Number: 18300015
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kumamoto University
• Principal Investigator: IIDA Masahiro Kumamoto University, 大学院・自然科学研究科, 准教授 (70363512)
• Co-Investigator(Kenkyū-buntansha): SUEYOSHI Toshinori 熊本大学, 大学院・自然科学研究科, 教授 (00117136)
• Project Period (FY): 2006 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥15,390,000 (Direct Cost: ¥12,900,000、Indirect Cost: ¥2,490,000); Fiscal Year 2008: ¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000); Fiscal Year 2007: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000); Fiscal Year 2006: ¥4,600,000 (Direct Cost: ¥4,600,000)
• Keywords: 設計自動化 / マルチコンテキスト / コンテキスト統合 / テクノロジマッピング / 配線共有 / FPGA / 低消費電力化 / クラスタリング / 構成データ

Research Abstract

本研究は,システムLSIに搭載されるプログラマブルロジックの実現に向けて,デバイス・アーキテクチャに即したEDAツールを開発することを目的とする. そして,それを用いることでシステムLSIの生産性の向上と多品種展開を実現する. 本研究で開発したEDAツールは,部分再構成,マルチコンテキスト、クラスタリングなど新しい機能を最大限に活用する統合EDAツールであり、これにより低消費電力化や高性能化を実現した

Research Products

• [Journal Article] An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture (2008)
  • Author(s): Motoki Amagasaki
  • Journal Title: International Journal of Reconfigurable Computing Vol. 2008
  • Peer Reviewed
• [Journal Article] Evaluating Variable-Grain Logic Cells using Heterogeneous Technology Mapping, P.C.Diniz et.al. (2007)
  • Author(s): Kazunori MATSUYAMA, Motoki AMAGASAKI, Hideaki NAKAYAMA, Ryoichi YAMAGUCHI, Masahiro IIDA, Toshinori SUEYOSHI
  • Journal Title: (eds.) : Reconfigurable Computing : Architectures, Tools and Applications, Lecture Notes in Computer Science (LNCS)4419, Springer-Verlag Berlin Heidelberg 4419 Pages: 142-154
  • Peer Reviewed
• [Journal Article] Clustering Technique to Reduce Chip Area and Delay for FPGA, (2007)
  • Author(s): M.Kobata, M.Iida and T.Sueyoshi
  • Journal Title: Electronics and Communications in Japan 6(Vol.90) Pages: 34-46
  • NAID: 110007385832
  • Peer Reviewed
• [Journal Article] A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices (2007)
  • Author(s): H.Shinohara, H.Monji, M.Iida and T.Sueyoshi
  • Journal Title: IEICE TRANSACTIONS on Information and Systems 12(vol.E90-D) Pages: 1986-1989
  • NAID: 110007538594
  • Peer Reviewed
• [Journal Article] A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices (2007)
  • Author(s): Hiroshi SHINOHARA
  • Journal Title: IEICE Transactions on Information and Systems E90-D Pages: 1986-1989
  • Peer Reviewed
• [Journal Article] Clustering Technique to Reduce Chip Area and Delay for FPGA (2007)
  • Author(s): Masaki KOBATA
  • Journal Title: Wiley Periodicals, Electronics and Communications in Japan, Part II 90 Pages: 34-46
  • Peer Reviewed
• [Journal Article] Evaluating Variable-Grain Logic Cells using Heterogeneous Technology Mapping (2007)
  • Author(s): Kazunori MATSUYAMA, Motoki AMABASAKI, Hideaki NAKAYAMA, Ryoichi YAMAGUCHI, Masahiro IIDA, Toshinori SUEYOSHI
  • Journal Title: Lecture Notes in Computer Science (LNCS), Springer-Verlag Berlin Heidelberg 4419 Pages: 142-154
• [Journal Article] 粒度可変構造を持つ再構成論理セル向けマッピング手法の評価 (2007)
  • Author(s): 山口良一, 中山英明, 尼崎太樹, 松山和憲, 飯田全広, 末吉敏則
  • Journal Title: 第14回FPGA/PLD Design Conference ユーザプレゼンテーション論文集 Pages: 25-32
• [Journal Article] FPGAのチップ面積および遅延を最適化するクラスタリング手法 (2006)
  • Author(s): 木幡雅貴, 飯田全広, 末吉敏則
  • Journal Title: 信学論 6(vol.J89-D) Pages: 1153-1162
  • Peer Reviewed
• [Journal Article] FPGAのチップ面積および遅延を最適化するクラスタリング手法 (2006)
  • Author(s): 木幡雅貴, 飯田全広, 末吉敏則
  • Journal Title: 電子情報通信学会論文誌 J89-D Pages: 1120-1129
• [Journal Article] 粒度可変構造を持つ再構成可能論理セル向けテクノロジマッピング手法 (2006)
  • Author(s): 中山英明, 山口良一, 尼崎太樹, 松山和憲, 飯田全広, 末吉敏則
  • Journal Title: 電子情報通信学会技術研究報告 RECONF2006-55 106・394 Pages: 67-72
  • NAID: 110005716988
• [Journal Article] 配線共有型マルチコンテキスト手法を用いた低消費電力化 (2006)
  • Author(s): 門司秀明, 篠原拓, 飯田全広, 末吉敏則
  • Journal Title: 電子情報通信学会技術研究報告 RECONF2006-50 106・394 Pages: 67-42
  • NAID: 110005716983
• [Journal Article] 粒度可変構造を持つ再構成論理セル向けマッピング手法の一検討 (2006)
  • Author(s): 山口良一, 松山和憲, 中山英明, 尼崎太樹, 飯田全広, 末吉敏則
  • Journal Title: 電子情報通信学会技術研究報告 RECONF2006-1(2006-05) 106・49 Pages: 1-6
  • NAID: 110004741126
• [Presentation] 粒度可変論理セルにおける入力粒度最適化の一検討 (2008)
  • Author(s): 古賀正紘
  • Organizer: 電子情報通信学会 リコフィギヤラブルシステム研究会
  • Place of Presentation: 岡山
  • Year and Date: 2008-09-26
• [Presentation] Efficient Permutation-based Boolean Matching for VGLC Technology Mapping (2008)
  • Author(s): Q. Zhao
  • Organizer: Joint Conference of Electrical and Electronics Engineers in Kyusyu
  • Place of Presentation: Oita
  • Year and Date: 2008-09-24
• [Presentation] Efficient Permutation-based Boolean Matching for VGLC Technology Mapping,'' Proc (2008)
  • Author(s): Q.Zhao, et.al.
  • Organizer: 2008 Joint Conference of Electrical and Electronics Engineers in Kyusyu
  • Place of Presentation: Oita, Japan
• [Presentation] A Boolean Matching Method for VGLC Technology Mapping, (2008)
  • Author(s): Qian Zhao,et.al.
  • Organizer: 情報処理学会九州支部若手の会セミナー
  • Place of Presentation: 福岡県
• [Presentation] A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic, '' Proc (2007)
  • Author(s): H.Shinohara, et.al.
  • Organizer: 15^<th> Annual IEEE Symposium on Field-programmable Custom Computing Machines (FCCM2007)
  • Place of Presentation: Napa, California
• [Presentation] An Implementation Technique for Variable Grain Logic Cell to Reduce Delay and Configuration Memories,'' Proc (2007)
  • Author(s): K.Matsuyama, et.al.
  • Organizer: 2007 Joint Conference of Electrical and Electronics Engineers in Kyusyu
  • Place of Presentation: Okinawa, Japan,
• [Presentation] A Context Design Method to Improve Power Efficiency for Reconfigurable Logic Device,'' Proc (2007)
  • Author(s): H.Shinohara, et.al.
  • Organizer: 2007 Joint Conference of Electrical and Electronics Engineers in Kyusyu
  • Place of Presentation: Okinawa, Japan,
• [Presentation] Evaluating Variable-Grain Logic Cells using Heterogeneous Technology Mapping,'' Proc (2007)
  • Author(s): K. Matsuyama, et.al.
  • Organizer: International Workshop on Applied Reconfigurable Computing (ARC2007)
  • Place of Presentation: Mangaratiba, Brazil
• [Presentation] FPGA向けクラスタリング及び配置における同時最適化手法の一検討 (2007)
  • Author(s): 篠原 拓, et.al.
  • Organizer: 信学技報, RECONF研究会
  • Place of Presentation: 立命館大学, 滋賀県
• [Presentation] 粒度可変構造を持つ再構成可能論理セル向けマッピング手法の評価 (2007)
  • Author(s): 山口良一, et.al.
  • Organizer: 第14回FPGA/PLD Design Conference,ユーザプレゼンテーション論文集
  • Place of Presentation: パシフィコ横浜, 神奈川県
• [Presentation] A Context Design Method to Improve Power Efficiency for Reconfigurable Logic Device (2007)
  • Author(s): Hiroshi SHINOHARA
  • Organizer: Joint Conference of Electrical and Electronics Engineers in Kyusyu
  • Place of Presentation: Okinawa,Japan
• [Presentation] A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic (2007)
  • Author(s): Hiroshi SHINOHARA
  • Organizer: IEEE Symposium on Field-programmable Custom Computing Machines (FCCM2007)
  • Place of Presentation: Napa,California,USA
• [Presentation] FPGA向けクラスタリング及び配置における同時最適化手法の一検討 (2007)
  • Author(s): 篠原 拓
  • Organizer: 電子情報通信学会 リコフィギャラブルシステム研究会
  • Place of Presentation: 滋賀県
• [Presentation] 粒度可変構造を持つ再構成論理セル向けマッピング手法の一検討 (2006)
  • Author(s): 山口良一, et.al.
  • Organizer: 信学技報, RECONF研究会
  • Place of Presentation: 東北大学, 宮城県,
• [Presentation] 配線共有型マルチコンテキスト手法を用いた低消費電力化 (2006)
  • Author(s): 門司秀明, et.al.
  • Organizer: 信学技報, RECONF研究会
  • Place of Presentation: 北九州国際会議場, 福岡県