| Project/Area Number |
18300020
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Osaka University |
|---|
Principal Investigator |
HIGASHINO Teruo Osaka University, Graduate School of lnformation Science and Technology, Professor (80173144)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
YASUMOTO Keiichi Nara Institute of Science and Teclmology, Graduate School ofInformation Science, Associate Professor (40273396)
NAKATA Akio Hiroshima Cotu University, Graduate School of Intrmation Sciences, Professor (60295839)
UMEDU Takaaki Osaka University, Graduate School ofIntonnation Science and Technology, Assistant Professor (10346174)
KITANI Tomoya Nara Institute of Science and lhchnology, Graduate School of Information Science, Assistant Professor (40418786)
|
|---|
| Project Period (FY) |
2006 – 2007
|
| Project Status |
Completed (Fiscal Year 2007)
|
| Budget Amount *help |
¥12,910,000 (Direct Cost: ¥11,200,000、Indirect Cost: ¥1,710,000)
Fiscal Year 2007: ¥7,410,000 (Direct Cost: ¥5,700,000、Indirect Cost: ¥1,710,000)
Fiscal Year 2006: ¥5,500,000 (Direct Cost: ¥5,500,000)
|
|---|
| Keywords | Ubiquitous Networks / Multi-Context / Network-on-Chip / Task Assignment / Sensor Devices / Task Scheduling / Routers / Real-Time Systems / Network on Chip (NoC) / 信頼性 / 動的再構成可能プロセッサ / 実時間システム / モデル検査 / 無線通信 |
|---|
| Research Abstract |
In this mearch, we have proposed a method for designing hardware circuits satisfying given network QoS constraints from a behavior specification on multi-context dynamically reconfigurable processor (DRP) and network-on-chip (NoC). We have also developed a circuit synthesis system based on the proposed method.
In the proposed method, we use a parametric model checking technique in order for generating the relation among parameters satisfying given network QoS constraints. From those parameter conditions and specification of multi-context dynamically reconfigurable processor (DRP), a suitable dynamically reconfigurable processor (DRP) is selected and the necessary tasks are automatically assigned into multiple contexts of the DRP. Depending on the given network QoS, the corresponding task scheduler is also automatically generated.
For a network-on-chip (NoC) architecture, we have also proposed a method for generating communication architecture among routers on the NoC and arranging the corresponding computing modules on the NoC mechanically.
Furthermore, we have proposed a certification technique for gathering encounter information anonymously and developed a small ubiquitous device for gathering encounter information. Based on the proposed technique, low-power small ubiquitous devices can be implemented.
|
