Design of highly reliable circuit considering crosstalk noise
| Project/Area Number |
18500040
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Tokyo Metropolitan University |
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Principal Investigator |
MIURA Yukiya Tokyo Metropolitan University, Graduate School of System Design, Associate Professor (00254152)
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| Project Period (FY) |
2006 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥1,350,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥150,000)
Fiscal Year 2007: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2006: ¥700,000 (Direct Cost: ¥700,000)
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| Keywords | Crosstalk / Dependable design / Synchronous circuits / Edge trigger clock / Level sensitive clock / Self-correction / Periodic signal |
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| Research Abstract |
In order to guarantee proper function of a system,a correct clock signal must be distributed. A crosstalk noise induced by a parasitic capacitance between signal lines gives a large influence to a digital circuit. This influence is called a crosstalk fault. Moreover,since synchronous digital circuits are the dominant technology in the present day,it is possible to cause incorrect behavior in many parts in the circuit when the crosstalk noise is generated on the clock signal line. It is difficult to eliminate perfect causes of crosstalk noises. Moreover,crosstalk noises are not always detected as faults,because their influence may cause behavior of intermittent faults and crosstalk noises happen accidentally by unintended causes. In this work,we proposed two methods for distributing the clock signal that take account of crosstalk noises generated on the clock signal line,which are applicable to conventional synchronous digital systems. For the clock signal of a pulse type,we proposed a double/multiple clock pulse method that has the tolerance for an incorrect clock pulse induced by a crosstalk fault. For the clock signal of a level sensitive type,we proposed a self-correction method for the change of the clock signal width during system operation. The proposed method does not require a reference signal for signal correction. The circuits implemented by both methods can be inserted into clock signal.lines as adapter circuits for the conventional clocked element and flip-flop,and as a result,the proposed methods are easily built in conventional synchronous digital circuits. From simulation results,we find that implemented circuits had the ability of the tolerance for the process variations. Two proposed methods are applicable to not only LSIs but also every synchronous circuit including board circuits. Besides,they are useful for circuits demanding high reliability.
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Report
(3 results)
Research Products
(20 results)
