Yield optimum layout generation under optical proximity effect

• Project/Area Number: 18560327
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: The University of Tokyo
• Principal Investigator: IKEDA Makoto The University of Tokyo, 大規模集積システム設計教育研究センター, 准教授 (00282682)
• Co-Investigator(Kenkyū-buntansha): SASAKI Masahiro 東京大学, 大規模集積システム設計教育研究センター, 助教 (50339701)
• Project Period (FY): 2006 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥4,030,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥630,000); Fiscal Year 2008: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2007: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000); Fiscal Year 2006: ¥1,300,000 (Direct Cost: ¥1,300,000)
• Keywords: 電子デバイス / 電子機器 / マスクレイアウト設計 / OPC / 網羅的セルレイアウト生成 / セルリーク電流最小化 / セル歩留まり / 焦点深度 / 露光時間 / セルレイアウト自動合成 / クリティカルエリア / レイアウト設計 / 光学近接効果 / 光学近接効果補正 / セルレイアウト / 歩留まり / 設計製造性

Research Abstract

集積回路の製造において用いられる微細なパターンの光転写において不可避となっている光学近接効果補正に対して、本研究では、設計パターンと製造されるパターンから逆問題を解くことにより補正を実施する手法の検討、パターン転写による製造不良を削減可能であることを示した。さらに、転写におけるばらつきがディジタル設計向けのセルにおける遅延、リークに与える影響の検討を行い、光学近接効果を考慮した場合のセルレイアウトの最適化によりセルのリーク電力低減に効果的であることを示した。

Research Products

• [Journal Article] A Temperature Sensor With an Inaccuracy of-1/+0.8℃ Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits (2008)
  • Author(s): M. Sasaki, M. Ikeda and K. Aasada
  • Journal Title: IEEE Transactions on Semiconductor Manufacturing Vol.21 Pages: 201-208
• [Journal Article] A Temperature Sensor With an Inaccuracy of -1/+0.8℃ Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits (2008)
  • Author(s): M. Sasaki M. Ikeda and K. Aasada
  • Journal Title: IEEE Transactions on Semiconductor Manufact uring 21 Pages: 201-208
  • Peer Reviewed
• [Journal Article] Timing-Aware Cell Layout De-Compactionfor Yield Optimization by Critical Area Minimization (2007)
  • Author(s): T. Iizuka, M. Ikeda and K. Asada
  • Journal Title: IEEE Transactions on Very Large Scale Integration(VLSI)Systems Vol.15, No.6 Pages: 716-720
• [Journal Article] Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization (2007)
  • Author(s): T. Iizuka, M. Ikeda and K. Asada,
  • Journal Title: IEEE Transactions on Very Large Scale Intergration(VLSI) Systems Vol.15,No.6 Pages: 716-720
  • Peer Reviewed
• [Presentation] Variation Tolerant Transceiver Design for System -on-Glass (2009)
  • Author(s): J. Kim J. Kim, K. Ikai, T. Nakura, M. Ikeda, K. Asada
  • Organizer: IEEE 34th European Solid-State Circuits Conference (ESSCIRC) Fringe
  • Place of Presentation: イギリス・エジンバラ
  • Year and Date: 2009-09-15
• [Presentation] Circuit Design using Stripe-Shaped TFTson Glass (2009)
  • Author(s): K. Ikai, J. Kim, M. Ikeda, and K. Asada
  • Organizer: IEEE Asia and South Pacific Design Automation Conference
  • Place of Presentation: Yokohama
  • Year and Date: 2009-01-20
• [Presentation] Circuit Design using Stripe (2009)
  • Author(s): K. Ikai, J. Kim, M. Ikeda, and K. Asada
  • Organizer: IEEE Asia and South Pacific Design Automati on Conference
  • Place of Presentation: 横浜市
  • Year and Date: 2009-01-20
• [Presentation] Variation Tolerant Transceiver Design for System-on-Glass (2008)
  • Author(s): J.Kim, K.Ikai, T.Nakura, M.Ikeda, K.Asada,
  • Organizer: IEEE 34th European Solid-State Circuits Conference(ESSCIRC)Fringe
  • Place of Presentation: Edinburgh,UK
  • Year and Date: 2008-09-15
• [Presentation] Delay Variation Measurements on DCVSL Using Logic Tester (2008)
  • Author(s): M. Ikeda
  • Organizer: University of Tokyo-UC Santa Barbara Joint Workshop
  • Place of Presentation: Santa Barbara, USA
  • Year and Date: 2008-09-08
• [Presentation] Delay Variation Measurements on DCVSL Using Logic Tester (2008)
  • Author(s): M. Ikeda
  • Organizer: University of Tokyo-UC Santa Barbara Joi nt Workshop
  • Place of Presentation: 米国・カリフォルニア州・サンタバーバラ市
  • Year and Date: 2008-09-08
• [Presentation] Process Variation Aware Comprehensive Layout Synthesis for YieldEnhancement in Nano-Meter CMOS (2007)
  • Author(s): K. Kurihara, T. Iizuka, M. Ikeda and K. Asada
  • Organizer: IEEE International Conference on Electronics, Circuits and Systems(ICECS)
  • Place of Presentation: Marrakech, Morocco
  • Year and Date: 2007-12-14
• [Presentation] Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-Meter CMOS (2007)
  • Author(s): M. Ikeda, K. Ishi, T. Sokabe and K. Asada
  • Organizer: IEEE International Conference on Electronics, Circuits and Systems(ICECS)
  • Place of Presentation: Marrakech, Morocco
  • Year and Date: 2007-12-12
• [Presentation] Datapath Delay Distributions for Data/Instruction Against PVT Variations in 90nm CMOS (2007)
  • Author(s): M. Ikeda, K. Ishi, T. Sokabe and K. Asada
  • Organizer: IEEE International Conference on Electronics, Circuits and Systems (ICECS)
  • Place of Presentation: Marrakech, Morrocco
  • Year and Date: 2007-12-12
• [Presentation] Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-Neter CMOS (2007)
  • Author(s): K. Kurihara, T. Iizuka, M. Ikeda and K. Asada
  • Organizer: IEEE International Conference on Electronics, Circuits and Systems (ICECS)
  • Place of Presentation: Marrakech, Morrocco
  • Year and Date: 2007-12-12
• [Presentation] 40 Frames/sec 16x16 Temperature Probe Array using 90nm 1V CMOS for On line Thermal Monitoring on VLSI Chip (2007)
  • Author(s): M. Sasaki, T. Inoue, M. Ikeda and K.Asada
  • Organizer: IEEE Asian Solid-State Circuits Conference(A-SSCC)
  • Place of Presentation: Jeju, Korea
  • Year and Date: 2007-11-14
• [Presentation] 40 Frames/sec 16×16 Temperature Probe Array using 90nm 1V CMOS for On line Thermal Monitoring on VLSI Chip (2007)
  • Author(s): M. Sasaki, T. Inoue, M. Ikeda and K. Asada
  • Organizer: IEEE Asian Solid-State Circuits Conference(A-SSCC)
  • Place of Presentation: Jeju, Korea
  • Year and Date: 2007-11-14
• [Presentation] Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology (2007)
  • Author(s): Z. Liang, M. Ikeda and K. Asada
  • Organizer: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems(DDECS)
  • Place of Presentation: Krakow,Poland
  • Year and Date: 2007-04-11
• [Presentation] Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology (2007)
  • Author(s): Z. Liang, M. Ikeda and K. Asada
  • Organizer: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
  • Place of Presentation: Krakow, Poland
  • Year and Date: 2007-04-11