| Budget Amount *help |
¥3,750,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥150,000)
Fiscal Year 2007: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2006: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Research Abstract |
1. In 2006, we obtained a prototype ADC chip which was fabricated by using 90 nm CMOS process. The fabrication run was supported by VDEC (University of Tbkyo). The ADC chip was in the 12-bit pipelined configuration that has been designed by using current-mode circuit techniques. The evaluated performances were a 2 V operation, a 25 MS/s speed, a 48 dB of Signal-to-Noise ratio, and an 8-bit accuracy. Low-voltage operation was OK, however, problems left are accuracy and speed.
2.The performance was moderate, however, the circuit technique was excellent and the future possibility to realize more high performance ADC was seen. The paper of this ADC was accepted to IEEE CICC and was presented in San Francisco in September, 2007.
3. Still, further study is necessary for realizing 10-bit accuracy with the clock speed of 100 MHz. Analyses have intensively done to find what were wrong for the prototype ADC not to be able to achieve the goal
One reason was in the clock driver part. The use of the termination resistor is preferable to make the ADC operate much faster than the prototype ADC.
The other reason was the design mistake in timing control of the sub-DAC iti a bit-block. Due to this, the gate voltage of current-mirror transistors became inactive on the transition of current change in the previous stage.
4. The circuit has been modified and simulated by using SPICE circuit simulation program in 2007, and 5 times of the improvement of linearity has been observed although it is the simulation basis. We started the circuit design again in the fall of 2007. Although we have not reached the layout stage of the re-designed ADC, we would like to have the 2nd version of ADC chip in 2008. We expect to have 10-bit accuracy and faster conversion rate than before.
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