| Project/Area Number |
18560355
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Ritsumeikan University |
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Principal Investigator |
FUJINO Takeshi Ritsumeikan University, Dept. of VLSI System Design, Professor (60367993)
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| Co-Investigator(Kenkyū-buntansha) |
YOSHIKAWA Masaya Meijyo University, Dept. of VLSI System Design, Associate Professor (50373098)
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| Project Period (FY) |
2006 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥3,880,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥480,000)
Fiscal Year 2007: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2006: ¥1,800,000 (Direct Cost: ¥1,800,000)
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| Keywords | Large Scale Integration / Advanced function device / Electron Beam Direct Writing / Programmable Logic / encryption, authentication / 先端機能デバイス |
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| Research Abstract |
Integrated electronic system composed of microprocessors and large memories can be realized as a single chip owing to the progress of micro-fabrication technology of VLSI. The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Electron Beam direct writing (EBDW) technology is the most cost-effective lithography tool, because it is mask-less technology. The EB exposure time will be greatly reduced by applying character-projection (CP) EB direct writing. So we have developed new LSI device architecture appropriate for this CP EB direct-writing.
In 2006, we proposed the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for CP EB direct writing.
In 2007, we compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. Furthermore we developed LSI test chip which applying VPEX architecture. The process technology used in this chip is 0.18 urn CMOS. We will evaluate this chip in the near future.
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