LSI Test Technology for Evaluating Soft-Error-Rates in Combinational Logic Circuits
| Project/Area Number |
18560359
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Japan Aerospace Exploration Agency |
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Principal Investigator |
KOBAYASHI Daisuke Japan Aerospace Exploration Agency, Institute of Space and Astronautical Science, Assistant Professor (90415894)
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| Co-Investigator(Kenkyū-buntansha) |
HIROSE Kazuyuki Institute of Space and Astronautical Science, 宇宙科学研究本部, Assistant Professor (00280553)
SAITO Hirobumi Institute of Space and Astronautical Science, 宇宙科学研究本部, Professor (80150051)
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| Project Period (FY) |
2006 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥3,660,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥360,000)
Fiscal Year 2007: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2006: ¥2,100,000 (Direct Cost: ¥2,100,000)
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| Keywords | Soft Errors / Single-Event Effects / Scan Designs / Design for Testability / Radiation / VLSIs / Combinational Circuits / SETs |
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| Research Abstract |
Very large scale integrations, VLSIs, exhibit transient errors called "soft errors" when exposed to radiation environments. As a result of aggressive miniaturization of transistors, the soft error is now becoming a serious failure source of logic VLSIs like CPUs. It is thus desired to evaluate experimentally soft-error rates of fabricated logic chips in irradiation tests. For the purpose, we have developed a new LSI test technology in this research project.
To evaluate soft-error rates of logic chips precisely, the following two requirements should he satisfied. Logic VLSIs consist of complicated networks of combinational logic circuits built with logic gates like inverters and sequential elements like flip-flops. It is required to count up the number of radiation-induced upsets of stored data at each sequential element scattered in the chips. Moreover, the data upsets are induced by not only direct radiation hits to the sequential elements and also latching pulse-type noises named "single-event transients, SETs, " which are generated by radiation hits to combinational logic circuits. The former is generally called "soft errors in sequential elements, " and the latter "soft errors in combinational logic circuits." It is now important to evaluate the impact of the soft errors in combinational logic circuits in particular. These both types of soft errors should be evaluated separately.
Our test technology is based on the scan test technology, which is widely used in today's logic chips for testing their operations because it enables us to write and read each sequential element directly. We have developed a scan flip- flop circuit and an irradiation test method for the soft-error rates evaluation. We have experimentally demonstrated the validity of the technology. Moreover, we have successfully revealed detailed pulse-width distributions of SETs in SOI-CMOS logic gates, and developed a fast and accurate estimation technique of SET waveforms.
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Report
(3 results)
Research Products
(47 results)
