Recearch on stereophonic acoustic echo canceller with both high sound quality and fast convergence speed
| Project/Area Number |
18560371
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Communication/Network engineering
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| Research Institution | Kanazawa University |
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Principal Investigator |
HIRANO Akihiro Kanazawa University, Graduate School of Natural Science and Technology, Assistant Professor (70303261)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAYAMA Kenji Kanazawa University, Graduate School of Natural Science and Technology, Professor (00207945)
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| Project Period (FY) |
2006 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥3,360,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥360,000)
Fiscal Year 2007: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2006: ¥1,800,000 (Direct Cost: ¥1,800,000)
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| Keywords | Echo Canceller / Multi-Channel / Uniaueness Problem |
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| Research Abstract |
1. Fast convergence algorithm by using two stereophonic acoustic echo cancellers (SAECs)
The distribution of the irregular solutions in the frequency domain has been analyzed. By estimating two independent irregular solutions and solving a simultaneous equation with four unknown variables, the distribution of all irregular solutions can be determined The optimum solution can be found by determining the irregular solutions for two talkers and solving another simultaneous equation with four unknown variables A fast convergence algorithm using two SAECs has been developed. Two irregular solutions can be estimated by using two SAECs with different initial coefficients. To estimate independent solutions, the independency is evaluated periodically. The SAECs are initialized when two solutions am not independent enough. A new initial value is so selected as to be orthogonal against another coefficient.
2. Real-time signal-processing systems
New real-time signal-processing systems with fist digital signal processors has been introduced.
3. Implementation of SAEC on Intel IA-32 Processors For low-cost PC-based teleconferencing, an SAEC has been implemented on Intel IA-32 processors. Some optimization have been carried out to use vector operations effectively. The optimized program is almost four times as fast as a conventional code.
4 Fast convergence algorithm by input-signal whitening
An improvement of the convergence speed has been studied which utilizes input-signal whitening. By modifying the locations of the whitening filters, the proposed algorithm dips not have to synchronize the main filter coefficients with those for the whitening filter as in the Lattice-based whitening method. Though this approach is effective when the number of taps is small, an improvement for a large number of taps should be a future study.
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Report
(3 results)
Research Products
(6 results)
