Fablication-friendly Configurable Processors in a nanometer LSI process

• Project/Area Number: 18680005
• Research Category: Grant-in-Aid for Young Scientists (A)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Kyoto University
• Principal Investigator: KOBAYASHI Kazutoshi Kyoto University, 情報学研究科, 准教授 (70252476)
• Project Period (FY): 2006 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥28,080,000 (Direct Cost: ¥21,600,000、Indirect Cost: ¥6,480,000); Fiscal Year 2008: ¥8,970,000 (Direct Cost: ¥6,900,000、Indirect Cost: ¥2,070,000); Fiscal Year 2007: ¥9,360,000 (Direct Cost: ¥7,200,000、Indirect Cost: ¥2,160,000); Fiscal Year 2006: ¥9,750,000 (Direct Cost: ¥7,500,000、Indirect Cost: ¥2,250,000)
• Keywords: ハードウエア設計 / 微細プロセス / プロセッサ / コンフィギャラブル / ばらつき / FPGA / Variation aware

Research Abstract

ばらつきを利用してコンフィギュラブルプロセッサなどの集積回路の特性向上を図るという研究提案に対し, プロセッサのソフトエラー対策を行なうという研究成果を得た. また, FPGAの配置を修正することで回路特性の向上を図るという研究成果も得た. 回路特性の劣化現象の対策, その解明に関する研究も行ない, 65nmプロセスによるLSIの試作, 測定も行なった.

Research Products

• [Journal Article] Micro/nanoimprinting of Glass under High Temperature Using a CVD Diamond Mold (2008)
  • Author(s): M. Komori, H. Uchiyama, H. Takebe, T. Kusuura, K. Kobayashi, H. Kuwahara, T. Tsuchiya
  • Journal Title: JOURNAL OF MICROMECHANICS AND MICROENGINEERING no.18 Pages: 65013-65013
  • Peer Reviewed
• [Journal Article] A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations (2007)
  • Author(s): K. Kobayashi, K. Katsuki, M. Kotani, Y.Sugihara, Y. Kume, H. Onodera
  • Journal Title: IEICE Trans. on Electronics vol.E90-C, no.10 Pages: 1919-1926
  • Peer Reviewed
• [Journal Article] A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations (2007)
  • Author(s): Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Journal Title: IEICE Trans. on Electronics vol.E90-C, no.4 Pages: 699-707
  • NAID: 110007522167
  • Peer Reviewed
• [Journal Article] A 90nm 48x48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations (2007)
  • Author(s): K. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, H. Onodera
  • Journal Title: IEICE Transacition on Electronics vol E90-C Pages: 1919-1926
  • Peer Reviewed
• [Journal Article] A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations (2007)
  • Author(s): K. Katsuki, M. Kotani, K. Kobayashi, H. Onodera
  • Journal Title: IEICE Transacition on Electronics vol E90-C Pages: 699-707
  • NAID: 110007522167
  • Peer Reviewed
• [Journal Article] A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations (2007)
  • Author(s): Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi
  • Journal Title: IEICE Trans.on Electronics Vol.E90-C, No.4 Pages: 699-707
  • NAID: 110007522167
• [Journal Article] A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations (2007)
  • Author(s): Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Journal Title: 12th Asia and South Pacific Design Automation Conference Pages: 122-123
• [Journal Article] A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era (2006)
  • Author(s): K. Kobayashi, A. Higuchi, H. Onodera
  • Journal Title: IEICE Transaction on Electronics vol.E89-C, no.6 Pages: 838-843
  • NAID: 110007503175
  • Peer Reviewed
• [Journal Article] A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era (2006)
  • Author(s): K.Kobayashi, A.Higuchi, H.Onodera
  • Journal Title: IEICE Transaction on Electronics Vol.E89-C, No.6 Pages: 838-843
  • NAID: 110007503175
• [Journal Article] A 90nm 8x16 LUT-based FPGA Enhancing Speed and Yield Utilizing Within-Die Variations (2006)
  • Author(s): M.Kotani, K.Katsuki, K.Kobayashi, H.Onodera
  • Journal Title: European Solid State Circuit Conference Pages: 110-113
• [Journal Article] A Yield and Speed Enhancement Technique Using Reconfigurable Devices against Within-Die Variations on (2006)
  • Author(s): K.Kobayashi, M.Kotani, et al.
  • Journal Title: International Conference on Field Programmable Logic and Applications Pages: 761-764
• [Presentation] Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration (2009)
  • Author(s): Y. Kume, Y. Sugihara, C. Ngo, K. Kobayashi, H. Onodera
  • Organizer: The 15th workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: Okinawa, Japan
  • Year and Date: 2009-03-09
• [Presentation] リーク電流によるNBTI特性の実測による評価 (2009)
  • Author(s): 牧野紘明、小林和淑、小野寺秀俊
  • Organizer: 2009年電子情報通信学会総合大会 エレクトロニクス講演論文集2,no.C-12-18, pp.106
  • Place of Presentation: 愛媛大学
• [Presentation] Soft-error Resiliency Evaluation on Delayed Multiple-modular Flip-Flops (2009)
  • Author(s): Jun Furuta, Yusuke Moritani, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)
• [Presentation] Embedded Delay Detectors to Choose the Fastest Route in FPGAs for Variation-aware Reconfiguration (2009)
  • Author(s): Yohei Kume, Yuuri Sugihara, Camlai Ngo, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: The 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009)
  • Place of Presentation: Okinawa, Japan
• [Presentation] A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs (2008)
  • Author(s): K. Kobayashi, Y. Kume, C. L. Ngo, Y. Sugihara, H. Onodera
  • Organizer: International Conference on Field Programmable Logic and Applications
  • Place of Presentation: Heidelberg, Germany
  • Year and Date: 2008-09-09
• [Presentation] Performance Optimization by Track.Swapping on Critical Paths Utilizing Random Variations for FPGAs (2008)
  • Author(s): Y. Sugihara, Y. Kume, K. Kobayashi. H. Onodera
  • Organizer: International Conference on Field Programmable Logic and_Applications
  • Place of Presentation: Heidelberg, Germany
  • Year and Date: 2008-09-09
• [Presentation] Best Ways to Use Billions of Devices on a Chip-Error Predictive, Defect Tolerant and Error Recovery Designs (2008)
  • Author(s): K. Kobayashi, K. Katsuki, M. Kotani, Y. Sugihara, Y. Kume, H.
  • Organizer: ASP-DAC
  • Place of Presentation: ソウル
  • Year and Date: 2008-01-25
• [Presentation] A Ring-Oscillator Array Circuit for Measurement and Modeling of Gate Delay Variability (2008)
  • Author(s): Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi. Hidetoshi Onodera
  • Organizer: Workshop on Test Structure Design for Variability Characterization
  • Place of Presentation: San Jose
• [Presentation] A Variation-aware Constant-Order Optimization Scheme Utilizing Delay Detectors to Search for Fastest Paths on FPGAs (2008)
  • Author(s): Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera
  • Organizer: 2008 Internation Conference on Field Programmable Logic and Applications
  • Place of Presentation: Heidelberg, Germany
• [Presentation] Performance Optimization by Track Swapping on Critical Paths Utilizing Random Variations for FPAs (2008)
  • Author(s): Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: 2008 International Conference on Field Programmable Logic and Applications
  • Place of Presentation: Heidelberg, Germany
• [Presentation] リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化 (2008)
  • Author(s): 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊
  • Organizer: DAシンポジウム2008
  • Place of Presentation: 浜松
• [Presentation] A Scalable Pipeline Design for Modularizing High Dependable Framework via Spatial Redundancy (2008)
  • Author(s): Jun Yao, Hajime Shimada, Kazutoshi Kobayashi
  • Organizer: DA Symposium 2008
  • Place of Presentation: Hamamatsu, Japan
• [Presentation] SETパルスによる誤動作を防止する遅延挿入フリップフロップのソフトエラー耐性の検討 (2008)
  • Author(s): 小林和淑, 森谷祐介, 小野寺秀俊
  • Organizer: DAシンポジウム2008
  • Place of Presentation: 浜松
• [Presentation] レイアウト規則性が回路性能とばらつきに及ぼす影響の評価 (2008)
  • Author(s): 砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊
  • Organizer: DAシンポジウム2008
  • Place of Presentation: 浜松
• [Presentation] 遅延比較器を用いた低コストなFPGAの速度・歩留まり向上手法 (2008)
  • Author(s): 久米洋平, 杉原有理, Ngo Cam Lai, 小林和淑, 小野寺秀俊
  • Organizer: 電子情報通信学会技術報告, vol.VLD2007-163, ICD-2007-186
  • Place of Presentation: 沖縄
• [Presentation] Speed and Yield Enhancement by Track Swaing on Critical Paths Utilizing Random Variations for FPGAs (2008)
  • Author(s): Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: FPGA
  • Place of Presentation: Monterey, California, USA
• [Presentation] Best Ways to Use Billions of Devices on a Chip - Error Predictive, Defect Tolerant and Error Recovery Designs (2008)
  • Author(s): Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: The 13th Asia and South Pacific Design Automation Conference
  • Place of Presentation: Seoul
• [Presentation] チップ内ばらつきを利用して歩留まりと速度を向上させるFPGA (2007)
  • Author(s): 久米洋平、杉原有理、香月和也、小林和淑、小野寺秀俊
  • Organizer: 第11回システムLSIワークショップ予稿集
  • Place of Presentation: 北九州国際会議場
• [Presentation] ランダムばらつきを利用したトラック入れ替えによるFPGAの速度と歩留まり向上 (2007)
  • Author(s): 杉原有理、久米洋平、小林和淑、小野寺秀俊
  • Organizer: 電子情報通信学会技術報告(RECONF2007-34),vol.107, no.340
  • Place of Presentation: 北九州国際会議場
• [Presentation] Estimation of Yield Enhancement by Critical Path Reconfiguration Utilizing Random Variations on Deep-submicron FPGAs, (2007)
  • Author(s): Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: SASIMI 2007
  • Place of Presentation: Sapporo, Japan
• [Presentation] 配線自由度によるばらつきを利用したFPGAの速度向上 (2007)
  • Author(s): 杉原有理、小林和淑、小野寺秀俊
  • Organizer: DAシンポジウム2007
  • Place of Presentation: 浜松
• [Presentation] 卓上テスト環境によるばらつき測定の高速化 (2007)
  • Author(s): 久米洋平, 小林和淑, 小野寺秀俊
  • Organizer: 電子情報通信学会総合大会予稿集
  • Place of Presentation: 名城大学
• [Presentation] A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations (2007)
  • Author(s): Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: 12th Asia and South Pacific Design Automation Conference
  • Place of Presentation: Yokohama
• [Presentation] ダイアモンドシールドを用いたガラスマイクロ・ナノインプリントの加工法の研究 (2006)
  • Author(s): 小森雅晴, 内山裕陽, 武部博倫, 楠浦崇央, 前川忠彦, 小林和淑
  • Organizer: 第6回生産加工・工作機械部門講演会講演論文集
  • Place of Presentation: 神奈川
• [Presentation] A 90nm 8x16 LUT-based FPGA Enhancing Speed and Yield Utilizing Within-Die Variations (2006)
  • Author(s): M. Kotani, K. Katsuki, K. Kobayashi, H. Onodera
  • Organizer: European Solid State Circuit Conference
  • Place of Presentation: Montreux, Switzerland
• [Presentation] 微細プロセスを用いたFPGA設計手法 (2006)
  • Author(s): 小林和淑
  • Organizer: 信学技報リコンフィギャラブルシステム,vol.106, no.246(RECONF 2006-26)
  • Place of Presentation: 熊本
• [Presentation] A Yield and Speed Enhancement Technique Using Reconfigurable Devices against Within-Die Variations on the Nanometer Regime (2006)
  • Author(s): K. Kobayashi, M. Kotani, K. Katsuki, Y. Takatsukasa, K. Ogata, Y. Sugihara, H. Onodera
  • Organizer: 2006 International Conference on Field Programmable Logic and Applications
  • Place of Presentation: Madrid, spain
• [Presentation] VDEC利用者から見たスターシャトル (2006)
  • Author(s): 小林和淑
  • Organizer: STARCフォーラム2006
  • Place of Presentation: 横浜
• [Presentation] FPGAのチップ内ばらつきを利用した再配置による高速化の検討 (2006)
  • Author(s): 尾形幸亮, 小谷学, 香月和也, 小林和淑, 小野寺秀俊
  • Organizer: 信学技報リコンフィギャラブルシステム,vol.106, no.50(RECONF2006-14)
  • Place of Presentation: 仙台
• [Presentation] チップ内ばらつきを考慮したFPGA内配線モデルの検討 (2006)
  • Author(s): 杉原有理, 高務祐哲, 小林和淑, 小野寺秀俊
  • Organizer: 第19回 回路とシステム軽井沢ワークショップ
  • Place of Presentation: 軽井沢プリンスホテル
• [Presentation] Extracting a Random Component of Variation from Measurement Results of a 90 nm LUT Array (2006)
  • Author(s): Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: SASIMI2006
  • Place of Presentation: Nagoya
• [Presentation] Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global Interconnect (2006)
  • Author(s): Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera
  • Organizer: SASIMI2006
  • Place of Presentation: Nagoya
• [Patent(Industrial Property Rights)] 半導体デバイス (2008)
  • Inventor(s): 小林和淑, 杉原有理, 久米洋平, 小野寺秀俊
  • Industrial Property Rights Holder: 国立大学法人京都大学
  • Industrial Property Number: 2008-026588
  • Filing Date: 2008-02-06
• [Patent(Industrial Property Rights)] 多重化実行に対してスケーラブルなプロセッサのパイプライン (2008)
  • Inventor(s): 嶋田創, 姚駿, 小林和淑
  • Industrial Property Rights Holder: 国立大学法人京都大学
  • Industrial Property Number: 2008-214900
  • Filing Date: 2008-08-25
• [Patent(Industrial Property Rights)] 半導体デバイス (2008)
  • Inventor(s): 小林和淑 他
  • Industrial Property Rights Holder: 京都大学
  • Industrial Property Number: 2008-026588
  • Filing Date: 2008-02-06