Research on Design for Testability for Multi-Clock Domain SoCs

• Project/Area Number: 18700046
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Nara Institute of Science and Technology
• Principal Investigator: YONEDA Tomokazu Nara Institute of Science and Technology, 情報科学研究科, 助教授 (20359871)
• Project Period (FY): 2006 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥3,810,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥210,000); Fiscal Year 2008: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2007: ¥700,000 (Direct Cost: ¥700,000); Fiscal Year 2006: ¥2,200,000 (Direct Cost: ¥2,200,000)
• Keywords: 設計自動化 / テスト容易化設計 / テストアーキテクチャ / テストスケジューリング / システムオンチップ / マルチクロックドメイン / ネットワークオンチップ

Research Abstract

プロセッサコア、機能コア、メモリコアなどのコア毎に異なるクロック周波数で動作するマルチクロックドメイン・システムオンチップに対するテスト容易化設計に関する研究を行った。その結果、高品質かつ高速テストを実現するための課題を明確化し、その課題を解決するテストアーキテクチャおよびテストスケジューリング手法の確立を行った。

Research Products

• [Journal Article] Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips (2008)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.10 Pages: 2440-2448
  • NAID: 10026805953
  • Peer Reviewed
• [Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time (2008)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.7 Pages: 1999-2007
  • NAID: 10026805015
  • Peer Reviewed
• [Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints (2008)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.7 Pages: 2008-2017
  • NAID: 10026805045
  • Peer Reviewed
• [Journal Article] Test Scheduling for Multi-Clock Domain SoCs under Power Constraint (2008)
  • Author(s): Tomokazu Yoneda, Kimihiko Masuda and Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.3 Pages: 747-755
  • NAID: 10026802150
  • Peer Reviewed
• [Journal Article] Effective Domain Partitioning for Multi-clock Domain IP Core Wrapper Design Under Power Constraints (2008)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.3 Pages: 807-814
  • NAID: 10026802270
  • Peer Reviewed
• [Journal Article] Scheduling power-constrained tests through the soc functional bus (2008)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.3 Pages: 736-746
  • NAID: 10026802124
  • Peer Reviewed
• [Journal Article] NoC-compatible wrapper design and optimization under channel bandwidth and test time constraints (2008)
  • Author(s): F. A. Hussin
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.7 Pages: 2008-2017
  • Peer Reviewed
• [Journal Article] On noc bandwidth sharing for the optimization of area cost and test application time (2008)
  • Author(s): F. A. Hussin
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.7 Pages: 1999-2007
  • Peer Reviewed
• [Journal Article] Thermal-aware test access mechanism and wrapper design optimization for system-on-chips (2008)
  • Author(s): T. E. Yu.
  • Journal Title: IEICE Transactions on Information and Systems Vol.E91-D, No.10 Pages: 2440-2448
  • Peer Reviewed
• [Journal Article] Scheduling power constrained tests through the soc functional bus (2008)
  • Author(s): F.A. Hussin, T. Yoneda, A. Orailoglu, H. Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol. E91-D, No. 3 Pages: 736-746
  • NAID: 10026802124
  • Peer Reviewed
• [Journal Article] Effective Domain Partitioning for Multi-clock Domain IP Core Wrapper Design Under Power Constraints (2008)
  • Author(s): T.E. Yu, T. Yoneda, D. Zhao, H. Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol. E91-D, No. 3 Pages: 807-814
  • NAID: 10026802270
  • Peer Reviewed
• [Journal Article] Test Scheduling for Multi-Clock Domain SoCs under Power Constraint (2008)
  • Author(s): T. Yoneda, K. Masuda, H. Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems Vol. E91-D, No. 3 Pages: 747-755
  • NAID: 10026802150
  • Peer Reviewed
• [Journal Article] NoC-compatible Wrapper Design and Optimization Under Channel Bandwidth and Test Time Constraints (2008)
  • Author(s): F.A. Hussin. T. Yoneda, H. Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems (To appear)
  • NAID: 10026805045
  • Peer Reviewed
• [Journal Article] On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time (2008)
  • Author(s): F.A. Hussin, T. Yoneda, H. Fujiwara
  • Journal Title: IEICE Transactions on Information and Systems (To appear)
  • NAID: 10026805015
  • Peer Reviewed
• [Journal Article] Core-based testing of multiprocessor system-on-chips utilizing hierarchical functional buses (2007)
  • Author(s): F.A.Hussin, T.Yoneda, A.Orailoglu, H.Fujiwara
  • Journal Title: Proceedings of the 12th Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07) Pages: 720-725
• [Journal Article] An soc test scheduling algorithm using reconfigurable union wrappers (2007)
  • Author(s): T.Yoneda, M.Imanishi, H.Fujiwara
  • Journal Title: Proceedings of the Design, Automation and Test in Europe (DATE' 07) Pages: 231-236
• [Journal Article] Using domain partitioning in wrapper design for IP cores under power constraints (2007)
  • Author(s): T.E.Yu, T.Yoneda, D.Zhao, H.Fujiwara
  • Journal Title: Proceedings of the IEEE 25th VLSI Test Symposium (VTS'07) (To appear)
• [Journal Article] TAM design and optimization for transparency-based soc test (2007)
  • Author(s): T.Yoneda, A.Shuto, H.Ichihara, T.Inoue, H.Fujiwara
  • Journal Title: Proceedings of the IEEE 25th VLSI Test Symposium (VTS'07) (To appear)
• [Journal Article] Power-aware multi-frequency heterogeneous soc test framework design with floor-ceiling packing (2007)
  • Author(s): D.Zhao, R.Huang, T.Yoneda, H.Fujiwara
  • Journal Title: Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007) (To appear)
• [Journal Article] Optimization of noc wrapper design under bandwidth and test time constraints (2007)
  • Author(s): F.A.Hussin, T.Yoneda, H.Fujiwara
  • Journal Title: Proceedings of the The IEEE European Test Symposium 2007 (To appear)
• [Journal Article] NoC wrapper optimization under channel bandwidth and test time constraints (2007)
  • Author(s): F.A.Hussin, T.Yoneda, H.Fujiwara
  • Journal Title: Technical Report of IEICE (DC2006-80) Vol. 106, No. 528 Pages: 1-6
  • NAID: 110006224499
• [Journal Article] Power-constrained SOC test schedules through utilization of functional buses (2006)
  • Author(s): F.A.Hussin, T.Yoneda, A.Orailoglu, H.Fujiwara
  • Journal Title: Proceedings of the 24th IEEE International Conference on Computer Design (ICCD'06) Pages: 230-236
• [Journal Article] Designing power-aware wrapper for multi-clock domain cores using clock domain partitioning (2006)
  • Author(s): T.E.Yu, T.Yoneda, D.Zhao, H.Fujiwara
  • Journal Title: Digest of Papers, IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06) Pages: 43-48
• [Journal Article] An optimal test bus design for transparency-based soc test (2006)
  • Author(s): T.Yoneda, A.Shuto, H.Ichihara, T.Inoue, H.Fujiwara
  • Journal Title: Digest of Papers, IEEE 7th Workshop on RTL and High Level Testing (WRTLT'06) Pages: 21-26
• [Journal Article] Power-conscious microprocessor-based testing of system-on-chip (2006)
  • Author(s): F.A.Hussin, T.Yoneda, A.Orailoglu, H.Fujiwara
  • Journal Title: Technical Report of IEICE (VLD2006-6) Vol. 106, No. 32 Pages: 25-30
  • NAID: 110004821860
• [Journal Article] メモリコアに対する組込み自己修復を考慮したSoCのテストスケジューリング (2006)
  • Author(s): 福田 雄介, 米田 友和, 藤原 秀雄
  • Journal Title: 信学技報(DC2006-48) Vol. 106, No. 387 Pages: 59-64
  • NAID: 110005717338
• [Presentation] Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints (2009)
  • Author(s): T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fuiiwara
  • Organizer: 14th Asia and South Pacific Design Automation Conference 2009 (ASP-DAC'09)
  • Place of Presentation: 横浜、神奈川
  • Year and Date: 2009-01-22
• [Presentation] Test Infrastructure Design for Core-Based System-on-Chip Under Cycle-Accurate Thermal Constraints (2009)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara
  • Organizer: 14th Asia and South Pacific Design Automation Conference (ASP-DAC2009)
• [Presentation] A reconfigurable wrapper design for multi-dock domain cores (2008)
  • Author(s): T. Yoshida, T. Yoneda and H. Fujiwara
  • Organizer: 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08)
  • Place of Presentation: 札幌、北海道
  • Year and Date: 2008-11-27
• [Presentation] マルチクロック・ドメイン・コアテストのための再構成可能ラッパーの一構成法 (2008)
  • Author(s): 吉田宜司, 米田友和, 藤原秀雄
  • Organizer: デザインガイア2008(ディペンダブルコンピューティング研究会)
  • Place of Presentation: 北九州学術研究都市、福岡
  • Year and Date: 2008-11-18
• [Presentation] Wrapper and TAM co-optimization for reuse of soc functional interconnects (2008)
  • Author(s): Tomokazu Yoneda and Hideo Fujiwara
  • Organizer: Design, Automation and Test in Europe (DATE'08)
• [Presentation] Wrapper and TAM co-optimization for reuse of soc functional interconnects (2008)
  • Author(s): T. Yoneda, H. Fujiwara
  • Organizer: Design, Automation and Test in Europe (DATE'08)
  • Place of Presentation: Munich, Germany
• [Presentation] Thermal-safe test access mechanism and wrapper co-optimization for system-on-chip (2007)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty and Hideo Fujiwara
  • Organizer: IEEE 16th Asian Test Symposium (ATS'07)
• [Presentation] Test scheduling for memory cores with built-in self-repair (2007)
  • Author(s): Tomokazu Yoneda, Yusuke Fukuda and Hideo Fujiwara
  • Organizer: IEEE 16th Asian Test Symposium (ATS'07)
• [Presentation] Area overhead and test time co-optimization through noc bandwidth sharing (2007)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara
  • Organizer: IEEE 16th Asian Test Symposium (ATS'07)
• [Presentation] Power-aware multi-frequency heterogeneous SoC test framework design with floor-ceiling packing (2007)
  • Author(s): Danella Zhao, Ronghua Huang, Tomokazu Yoneda, and Hideo Fujiwara
  • Organizer: 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
• [Presentation] Optimization of noc wrapper design under bandwidth and test time constraints (2007)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda and Hideo Fujiwara
  • Organizer: The IEEE European Test Symposium 2007 (ETS'07)
• [Presentation] TAM design and optimization for transparency-based soc test (2007)
  • Author(s): Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara
  • Organizer: IEEE 25th VLSI Test Symposium (VTS'07)
• [Presentation] Using domain partitioning in wrapper design for IP cores under power constraints (2007)
  • Author(s): Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao and Hideo Fujiwara
  • Organizer: IEEE 25th VLSI Test Symposium (VTS'07)
• [Presentation] Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses (2007)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, and Hideo Fujiwara
  • Organizer: 12th Asia and South Pacific Design Automation Conference 2007 (ASP-DAC'07)
• [Presentation] An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers (2007)
  • Author(s): Tomokazu Yoneda, Masahiro Imanishi and Hideo Fujiwara
  • Organizer: Design, Automation and Test in Europe (DATE'07)
• [Presentation] An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers (2007)
  • Author(s): T. Yoneda, M. Imanishi, H. Fujiwara
  • Organizer: Design, Automation and Test in Europe (DATE'07)
  • Place of Presentation: Nice, France
• [Presentation] Using domain partitoning in wrapper design for IP cores under power constraints (2007)
  • Author(s): T.E. Yu, T. Yoneda, D. Zhao, H. Fujiwara
  • Organizer: IEEE 25th VLSI Test Symposium (VTS'07)
  • Place of Presentation: Berkekey, USA
• [Presentation] TAM design and optimization for transparency-based soc test (2007)
  • Author(s): T. Yoneda, A. Shuto, H. Ichihara, T. Inoue, H. Fujiwara
  • Organizer: IEEE 25th VLSI Test Symposium (VTS'07)
  • Place of Presentation: Berkekey, USA
• [Presentation] Optimization of noc wrapper design under bandwidth and test time constraints (2007)
  • Author(s): F.A. Hussin, T. Yoneda, H. Fujiwara
  • Organizer: The IEEE European Test Symopsium 2007 (ETS'07)
  • Place of Presentation: Freiburg, Germany
• [Presentation] Poweraware multi-frequency heterogeneous SoC test framework designwith floor-ceiling packing (2007)
  • Author(s): D. Zhao, R. Huang, T. Yoneda, H. Fujiwara
  • Organizer: 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
  • Place of Presentation: New Orleans, USA
• [Presentation] Area overhead and test time co-optimization through noc bandwidth sharing (2007)
  • Author(s): F.A. Hussin, T. Yoneda, H. Fujiwara
  • Organizer: IEEE 16th Asian Test Symopsium (ATS'07)
  • Place of Presentation: Beijing, China
• [Presentation] Test scheduling for memory cores with built-in self-repair (2007)
  • Author(s): T. Yoneda, Y. Fukuda, H. Fujiwara
  • Organizer: IEEE 16th Asian Test Symposium (ATS'07)
  • Place of Presentation: Beijing, China
• [Presentation] Power-constrained SOC test schedules through utilization of functional buses (2006)
  • Author(s): Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu and Hideo Fujiwara
  • Organizer: 24th IEEE International Conference on Computer Design (ICCD'06)