Demonstration of wiring-driven integrated circuit system design theory utilizing multi-valued data transmission
| Project/Area Number |
18H01488
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Review Section |
Basic Section 21060:Electron device and electronic equipment-related
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| Research Institution | Gunma University |
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Principal Investigator |
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| Project Period (FY) |
2018-04-01 – 2022-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥12,610,000 (Direct Cost: ¥9,700,000、Indirect Cost: ¥2,910,000)
Fiscal Year 2020: ¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2019: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2018: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
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| Keywords | 高速信号伝送 / 多値論理 / 波形等化回路 / PAM-4 / イコライザ / 符号化技術 / 高速インタフェース / 多値情報処理 / 等化回路 / 情報通信工学 / 高速伝送回路設計 / 波形等化技術 / FPGA |
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| Outline of Final Research Achievements |
In order to realize data communication in VLSI systems and data centers, etc., where higher speeds and capacities are required, this research examined the construction of a new concept of high-speed data transmission system design theory utilizing devices with multi-level coding, which is used in the next-generation high-speed data communication standards. In particular, "Waveform equalization techniques specific to 4-level signals" and "Eye-pattern evaluation of received signals" were studied. As research results, we developed elemental technologies such as digital-rich waveform equalization circuits, coding, and pre-distortion as waveform shaping technologies for PAM-4 data transmission, enabling evaluation of each technology on actual transmission lines and making it effective for testing multi-valued data transmission systems.
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| Academic Significance and Societal Importance of the Research Achievements |
現在、VLSIシステムやデータセンター等において高速大容量データ伝送のニーズが高まっているが、配線の激増・伝送波形の劣化等が課題となっている。それに対し、無線通信で用いられている高度な符号化・信号処理技術が信号伝送の高性能化に適用可能な点に着目し、配線主体のVLSIシステムの設計理論体系を構築する点が本研究の学術的意義となる。
本研究成果は、微細化集積回路において、従来のデバイス主体の設計とは異なり、配線の高性能化に着目することによりデバイス性能を活かす新視点の集積回路設計手法であり、高速高効率データ伝送を目的としたVLSIシステム、データセンター等のインフラ実現に有効な技術と考えられる。
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Report
(4 results)
Research Products
(26 results)
