High quality Ge-based transistor using epitaxially grown high-k gate insulators
| Project/Area Number |
18K04235
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 21050:Electric and electronic materials-related
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| Research Institution | Osaka University |
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Principal Investigator |
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| Project Period (FY) |
2018-04-01 – 2022-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2021: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2020: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2019: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2018: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
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| Keywords | Ge-MISFET / La2O3 / 原子マッチング / 結晶転位 / 接触角 / ラジカル処理 / エピタキシャル絶縁膜 / 基板欠陥 / La2O2 / 直接接合 / エピタキシャルゲート絶縁膜 / パルスレーザ蒸着法 / 界面準位密度 / 低温成長 / high-k/Ge / ゲルマニウム半導体 / エピタキシャル成長 / 界面 |
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| Outline of Final Research Achievements |
Germanium (Ge)-MISFETs using low-temperature growth epitaxial La2O3 as a gate insulating film have been focused. The gate-stack is formed directly on Ge with low interface defects by atomic matching without a GeO2 buffer layer which is thermally unstable and relatively low dielectric constant. Therefore, it can reduce the oxide film equivalent film thickness (EOT) for further miniaturization. In order to improve the interface characteristics, the iodine solution treatment is optimized as surface passivation and the Ge-based transistor fabrication process is optimized. As a result, relatively high mobility of the Ge-MOSFET fabricated at a low temperature of 350 oC is achieved. Moreover, in order to realize a smaller EOT, the interface reaction was suppressed by controlling the oxygen concentration during growth and optimizing the annealing conditions.
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| Academic Significance and Societal Importance of the Research Achievements |
本研究では，次世代半導体材料として有望視されているゲルマニウム（Ge）に格子マッチングするLa2O3ゲート絶縁膜を組み合わせ，新たに提案した基板表面処理，および界面反応を抑制することで，高品質なゲートスタックを形成できることを示した．これは，全結晶材料MISFETへの道への開拓と繋がる．そして，既にエピタキシャル積層構造を実証しつつあるように，今までは困難であった Ge(111) 上へのゲート絶縁膜上に，さらなる機能性結晶材料をエピタキシャルに積層することで，新たな機能の発現や，半導体材料を積層成長させることで，縦型(3D)構造による超高集積化など，更なる機能改善へと展開が期待される．
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Report
(5 results)
Research Products
(4 results)
