| Project/Area Number |
18K11213
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 60040:Computer system-related
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| Research Institution | Mie University (2019-2020)
Kyoto University (2018) |
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Principal Investigator |
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| Project Period (FY) |
2018-04-01 – 2021-03-31
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| Project Status |
Completed (Fiscal Year 2020)
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| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2020: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2019: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2018: ¥520,000 (Direct Cost: ¥400,000、Indirect Cost: ¥120,000)
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| Keywords | 論理回路 / 超伝導単一磁束量子デバイス / 設計自動化 / テストパタン生成 / タイミング故障 / LSI設計技術 / 超伝導単一磁束量子回路 / 信頼性 / 集積回路のテスト |
|---|
| Outline of Final Research Achievements |
Rapid Single-Flux-Quantum logic circuits operate based on pulse logic at high-speed. To design reliable circuits, we developed automatic placement and routing methods that satisfy the timing constraints for correct operation.
We defined a timing fault as an event that pulse arrival at a logic gate in the fabricated chip is delayed or advanced with respect to the cycle assumed in the design. We proposed an algorithm to generate test pattern sequences to detect timing faults.
We developed methods for logic simulation and automatic routing by applying our knowledge related to the operation timing of rapid single-flux-quantum circuits obtained through the research task.
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| Academic Significance and Societal Importance of the Research Achievements |
超伝導デバイス技術が進歩し、大規模単一磁束量子回路の試作が進められている。単一磁束量子回路による、半導体CMOS論理回路より高速で低消費電力の論理回路の実現可能性が示されている。大規模回路の実現と高性能化のためには、デバイス技術とともに設計自動化技術が不可欠である。本研究のテスト手法および回路の高信頼化技術は、これまでに開発した設計支援技術と合わせて、超伝導デバイスのディジタル応用に貢献すると考えられる。
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