• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Studies on Reliability Enhancement of Reconfigurable Integrated Circuits in the IoT Era

Research Project

Project/Area Number 18K11220
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 60040:Computer system-related
Research InstitutionOita University

Principal Investigator

Ohtake Satoshi  大分大学, 理工学部, 教授 (20314528)

Project Period (FY) 2018-04-01 – 2024-03-31
Project Status Completed (Fiscal Year 2023)
Budget Amount *help
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2020: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2019: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Keywords再構成可能集積回路 / 劣化検知機構 / 高信頼化設計 / 動的回路再構成 / 劣化情報取得 / 信頼性予測 / 集積回路 / 高信頼化 / FPGA / フィールドテスト / FPGA高信頼化
Outline of Final Research Achievements

In reconfigurable integrated circuits such as Field Programmable Gate Arrays (FPGAs), if the degradation status of circuit elements can be determined, it is possible to synthesize circuit configuration that avoids its impact and achieve high reliability by reprogramming the configuration according to the degradation status. To achieve this, this study focused on three aspects: (1) embedding degradation detection test mechanisms from high-level design, (2) acquiring degradation information and predicting reliability, and (3) synthesizing configuration with high reliability using degradation information. As research outcomes, we have proposed degradation detection mechanisms on FPGAs, have evaluated the acquisition of degradation information and predict reliability using the proposed mechanisms, and have proposed a method for generating circuit configuration information using the degradation information.

Academic Significance and Societal Importance of the Research Achievements

FPGA上での劣化検知機構の提案と実証により,回路素子の劣化状況を正確に把握する技術が進展した。動的に回路を再構成する手法が確立されたことにより,長期間の運用でも高信頼性を維持する設計が実現される。
提案した技術により,FPGAを用いたシステム全体の信頼性が向上する。これにより,産業用機器や医療機器,通信インフラなどの重要な分野でのFPGAを用いたシステムの長期的な安定運用が期待される。動的に回路を再構成することで高信頼性のシステムを構築でき,機器の寿命が延び,廃棄される電子機器の量が減少する。これにより環境負荷の軽減に寄与することも期待される。

Report

(7 results)
  • 2023 Annual Research Report   Final Research Report ( PDF )
  • 2022 Research-status Report
  • 2021 Research-status Report
  • 2020 Research-status Report
  • 2019 Research-status Report
  • 2018 Research-status Report
  • Research Products

    (8 results)

All 2023 2021 2019 2018

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (5 results) (of which Int'l Joint Research: 1 results) Patent(Industrial Property Rights) (1 results)

  • [Journal Article] Hardware Implementation of Constant Monitoring System of Fetal Heart Sounds2023

    • Author(s)
      Funakoshi Miyabi, Satoshi Ohtake
    • Journal Title

      2023 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)

      Volume: - Pages: 663-664

    • DOI

      10.1109/icce-taiwan58799.2023.10227017

    • Related Report
      2023 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures2019

    • Author(s)
      Hiramoto Yushiro、Ohtake Satoshi、Takahashi Hiroshi
    • Journal Title

      Proceedings of IEEE 28th Asian Test Symposium

      Volume: - Pages: 31-36

    • DOI

      10.1109/ats47505.2019.000-4

    • Related Report
      2019 Research-status Report
    • Peer Reviewed
  • [Presentation] 胎児心音常時モニタリングシステムのハードウェア実装2023

    • Author(s)
      舩越雅,大竹哲史
    • Organizer
      火の国情報シンポジウム
    • Related Report
      2022 Research-status Report
  • [Presentation] SATを用いた遅延故障BIST向けLFSRシード生成法2021

    • Author(s)
      岩本岬汰郎,大竹哲史
    • Organizer
      電子情報通信学会
    • Related Report
      2021 Research-status Report
  • [Presentation] 遅延故障向け組込み自己診断のための圧縮シード生成法2019

    • Author(s)
      中野雄太,大竹哲史
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Related Report
      2019 Research-status Report
  • [Presentation] Compacted Seed Generation for Built-in Self-Diagnosis of Delay Faults2019

    • Author(s)
      Yuta Nakano, Satoshi Ohtake
    • Organizer
      IEEE Workshop on RTL and High Level Testing
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] 期待署名自己生成に基づく組込み自己診断機構2018

    • Author(s)
      平本悠翔郎, 大竹哲史, 高橋 寛
    • Organizer
      電子情報通信学会ディペンダブルコンピューティング研究会
    • Related Report
      2018 Research-status Report
  • [Patent(Industrial Property Rights)] 回路診断テスト装置、及び回路診断テスト方法2019

    • Inventor(s)
      大竹哲史,平本悠翔郎
    • Industrial Property Rights Holder
      大分大学
    • Industrial Property Rights Type
      特許
    • Industrial Property Number
      2019-027786
    • Filing Date
      2019
    • Related Report
      2018 Research-status Report

URL: 

Published: 2018-04-23   Modified: 2025-01-30  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi