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Research on LSI design methods to identify Trojan circuits in IP cores

Research Project

Project/Area Number 18K11228
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 60040:Computer system-related
Research InstitutionKyoto Sangyo University

Principal Investigator

Yoshimura Masayoshi  京都産業大学, 情報理工学部, 准教授 (90452820)

Co-Investigator(Kenkyū-buntansha) 細川 利典  日本大学, 生産工学部, 教授 (40373005)
Project Period (FY) 2018-04-01 – 2023-03-31
Project Status Completed (Fiscal Year 2022)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2020: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2019: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Keywordsトロイ回路 / ブラックボックス / ホワイトボックス / SATソルバー / モンテカルロツリーサーチ / 入力系列生成 / IPコア / 内部状態 / 到達不能状態 / ハードウェアトロイ回路 / 等価性検証
Outline of Final Research Achievements

We have developed a technique to detect trojan circuits that may be included in IP cores, which are LSI design data. Trojan circuits that are activated in states that are rarely used during operation are difficult to detect in the LSI desgin phases. To detect these states, we developed a method using a SAT solver and Monte Carlo tree search. For small and medium benchmark circuits, we were able to identify these states with high accuracy in a relatively short time. On the other hand, search times for large benchmark circuits were long.

Academic Significance and Societal Importance of the Research Achievements

情報化社会において,LSIは基盤となる部品であり,LSIの信頼性や安全性が損なわれると,情報化社会の信頼性安全性にも大きな影響を与える.本研究は,LSIの信頼性と安全性をLSI設計レベルで高める技術である.本研究は,LSIの設計段階において,LSIに悪意のある回路が含まれていないかの判定に用いられる.LSIへの悪意のある回路の混入を防ぐことで,情報化社会の信頼性と安全性の向上に貢献する.

Report

(6 results)
  • 2022 Annual Research Report   Final Research Report ( PDF )
  • 2021 Research-status Report
  • 2020 Research-status Report
  • 2019 Research-status Report
  • 2018 Research-status Report
  • Research Products

    (24 results)

All 2022 2021 2020 2019 2018

All Journal Article (3 results) (of which Peer Reviewed: 3 results) Presentation (21 results) (of which Int'l Joint Research: 9 results)

  • [Journal Article] A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns2018

    • Author(s)
      Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura
    • Journal Title

      2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)

      Volume: 24 Pages: 228-231

    • DOI

      10.1109/iolts.2018.8474097

    • Related Report
      2018 Research-status Report
    • Peer Reviewed
  • [Journal Article] A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification2018

    • Author(s)
      Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
    • Journal Title

      2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)

      Volume: 24 Pages: 43-46

    • DOI

      10.1109/iolts.2018.8474268

    • Related Report
      2018 Research-status Report
    • Peer Reviewed
  • [Journal Article] A Capture Safe Static Test Compaction Method Based on Don't Cares2018

    • Author(s)
      Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
    • Journal Title

      2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)

      Volume: 24 Pages: 195-200

    • DOI

      10.1109/iolts.2018.8474080

    • Related Report
      2018 Research-status Report
    • Peer Reviewed
  • [Presentation] CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level2022

    • Author(s)
      Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, and Toshinori Hosokawa
    • Organizer
      2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 無効状態を含んだコントローラの遷移故障検出率向上指向状態割当て法2022

    • Author(s)
      飯塚恭平, 細川利典, 山崎紘史, 吉村正義
    • Organizer
      ディペンダブルコンピューティング研究会
    • Related Report
      2021 Research-status Report
  • [Presentation] 論理故障テスト並列化のための制御信号のドントケア割当て法2022

    • Author(s)
      徐 浩豊, 細川利典, 山崎紘史, 新井雅之, 吉村正義
    • Organizer
      ETNET2022
    • Related Report
      2021 Research-status Report
  • [Presentation] An Additional State Transition Insertion Method to Improve Transition Fault Coverage for Controllers2021

    • Author(s)
      Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki and Masayoshi Yoshimura
    • Organizer
      IEEE The Workshop on RTL and High Level Testing 2021
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] 低消費電力指向多重目標故障テスト生成法2021

    • Author(s)
      三浦 怜, 細川利典, 山崎紘史, 吉村正義, 新井雅之
    • Organizer
      第6回 Winter Workshop on Safety
    • Related Report
      2021 Research-status Report
  • [Presentation] RTLハードウェア要素のテストスケジューリング情報を用いた多重目標故障テスト生成法2021

    • Author(s)
      浅見竜輝・細川利典・山崎紘史・吉村正義・新井雅之
    • Organizer
      ディペンダブルコンピューティング研究会
    • Related Report
      2020 Research-status Report
  • [Presentation] レジスタ転送レベルにおける非スキャンベースフィールドテスタビリティに基づく制御信号のドントケア割当て法2021

    • Author(s)
      飯塚恭平・細川利典・山崎紘史・吉村正義
    • Organizer
      ディペンダブルコンピューティング研究会
    • Related Report
      2020 Research-status Report
  • [Presentation] コントローラの遷移故障検出率向上のためのコントローラ拡大法2021

    • Author(s)
      飯塚恭平・細川利典・山崎紘史・吉村正義
    • Organizer
      ETNET2021
    • Related Report
      2020 Research-status Report
  • [Presentation] レジスタ転送レベルにおけるアンチSATに基づく論理暗号化法2021

    • Author(s)
      辻川敦也・細川利典・吉村正義
    • Organizer
      ETNET2021
    • Related Report
      2020 Research-status Report
  • [Presentation] A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method2020

    • Author(s)
      Toshinori HOSOKAWA, Kenichiro MISAWA, Hiroshi YAMAZAKI, Masayoshi YOSHIMURA, Masayuki ARAI
    • Organizer
      2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS)
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Presentation] テストパターン数削減のためのゲート網羅故障の多重目標故障テスト生成法2020

    • Author(s)
      浅見竜輝・細川利典・吉村正義・新井雅之
    • Organizer
      SWoPP2020
    • Related Report
      2020 Research-status Report
  • [Presentation] 機能等価な有限状態機械生成に基づく面積削減指向コントローラ拡大法2020

    • Author(s)
      辻川敦也・細川利典・吉村正義
    • Organizer
      SWoPP2020
    • Related Report
      2020 Research-status Report
  • [Presentation] A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT2020

    • Author(s)
      Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai
    • Organizer
      2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths2019

    • Author(s)
      Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, and Masayoshi Yoshimura
    • Organizer
      2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] A State Assignment Method to Improve Transition Fault Coverage for Controllers2019

    • Author(s)
      Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, and Masavuki Arai
    • Organizer
      2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] A State Assignment Method to Improve Transition Fault Coverage for Controllers2019

    • Author(s)
      Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki and Toshinori Hosokawa
    • Organizer
      2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Don't Care Identification-Filling Co-Optimization Method for Low Capture Power Testing Using Partial MaxSAT2019

    • Author(s)
      Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura, and Masayuki Arai
    • Organizer
      The 20th Workshop on RTL and High-Level Testing (WRTLT’19)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] レジスタ転送レベルにおけるコントローラ拡大を用いた遷移故障検出率向上のためのテスト容易化設計2018

    • Author(s)
      竹内勇希、細川利典、山崎紘史、吉村正義
    • Organizer
      DAシンポジウム2018
    • Related Report
      2018 Research-status Report
  • [Presentation] A design for testability method to improve transition fault coverage using controller augmentation at register transfer level2018

    • Author(s)
      Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki , Masayoshi Yoshimura
    • Organizer
      The Nineteenth Workshop on RTL and High Level Testing
    • Related Report
      2018 Research-status Report
    • Int'l Joint Research
  • [Presentation] キャプチャセーフテストベクトルの故障伝搬経路を模倣した低消費電力指向ドントケア判定法2018

    • Author(s)
      三澤健一郎・細川利典・山崎紘史・吉村正義
    • Organizer
      ディペンダブルコンピューティング研究会
    • Related Report
      2018 Research-status Report
  • [Presentation] コントローラの遷移故障検出率向上のための状態割当て手法2018

    • Author(s)
      吉村正義・竹内勇希・細川利典・山崎紘史
    • Organizer
      ディペンダブルコンピューティング研究会
    • Related Report
      2018 Research-status Report

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Published: 2018-04-23   Modified: 2024-01-30  

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