HDLRuby: a new high productivity hardware description language targeting next generation edge computing architectures for IoT
| Project/Area Number |
18K11284
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 60060:Information network-related
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| Research Institution | Ariake National College of Technology |
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Principal Investigator |
Gauthier Lovic 有明工業高等専門学校, 創造工学科, 准教授 (90535717)
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| Co-Investigator(Kenkyū-buntansha) |
石川 洋平 有明工業高等専門学校, 創造工学科, 准教授 (50435476)
白鳥 則郎 中央大学, 研究開発機構, 機構教授 (60111316)
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| Project Period (FY) |
2018-04-01 – 2022-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2021: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2020: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2019: ¥520,000 (Direct Cost: ¥400,000、Indirect Cost: ¥120,000)
Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | ハードウエア記述言語 / デジタル回路 / エッジコンピューティング / Ruby言語 / コンパイラー / シミュレータ / HDL / Edge Computing / FPGA / Design Exploration / Simulation / Ruby Language / HW design / Framework / Libraries / Evaluation / Edgfe computing / Neural network / Translation / HW simulation / Edge computing / IoT / Productivity |
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| Outline of Final Research Achievements |
This research project aimed to develop and promote HDLRuby, a language for designing digital circuits. The goal was to increase the productivity of designers implementing edge-computing applications. Toward that end, this language has been developed from a prototype to a ready-to-use framework for the fast design of digital circuits.
HDLRuby being a new language, it is not directly supported by existing digital circuit synthesis tools. Hence, the framework includes a compiler for converting HDLRuby descriptions into synthesizable code in standard languages (Verilog HDL and VHDL). A simulator is also provided for validating the HDLRuby descriptions before the corresponding circuit is being implemented, and a library of generic components for shorter descriptions of complex circuits. The HDLRuby framework has been validated with the implementation of several circuits, and it has been made publicly available online as standard packages and as a source code repository.
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| Academic Significance and Societal Importance of the Research Achievements |
IoTを実現するために情報処理をセンサーとアクチュエータに近づくエッジコンピューチングはエネルギー消費やセキュリティに対してメリットが多い．ただし，そのようなシステムには複数のデジタル回路が必要であり，それらの設計は時間がかかる．そのために，本研究ではHDLRubyと呼ばれたデジタル回路の設計の生産力を向上する新しい言語と設計フレームワークを開発した．HDLRubyは多数の回路の実装で検証されており，パッケージ及びソースコードリポジトリとしてネットで公開されている．
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Report
(5 results)
Research Products
(42 results)
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[Journal Article] Federated Learning with Divided Data for BP2021
Author(s)
Hirofumi Miyajima, Noritaka Shigei, Hiromi Miyajima, Norio Shiratori
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Journal Title
Proceedings of the International MultiConference of Engineers and Computer Scientists 2021
Volume: 28
Pages: 94-99
Related Report
Peer Reviewed / Open Access / Int'l Joint Research
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