Response Prediction for Packet Processing Caches

• Project/Area Number: 18K18022
• Research Category: Grant-in-Aid for Early-Career Scientists
• Allocation Type: Multi-year Fund
• Review Section: Basic Section 60040:Computer system-related
• Research Institution: The University of Electro-Communications
• Principal Investigator: Yamaki Hayato 電気通信大学, 大学院情報理工学研究科, 助教 (20782197)
• Project Period (FY): 2018-04-01 – 2021-03-31
• Project Status: Completed (Fiscal Year 2020)
• Budget Amount: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000); Fiscal Year 2020: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2019: ¥520,000 (Direct Cost: ¥400,000、Indirect Cost: ¥120,000); Fiscal Year 2018: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
• Keywords: インターネットルータ / パケット処理キャッシュ / 省電力 / 高スループット / パケット予測 / TCAM / パケット予測処理 / パケット処理 / 初期参照ミス / ルータ / キャッシュ / データ予測

Outline of Final Research Achievements

In this research, we proposed a packet prediction method for PPCs (Packet Processing Caches), which increased the table-lookup throughput of an Internet router and reduced its power consumption. The method predicts packets which may arrive in the near future and caches their table lookup results by executing the table lookups in advance. As a result of this research, it was shown that the proposed method can achieve 1.38x table-lookup throughput with 74% power consumption compared to the conventional PPCs when the proposed method was adopted to the multi-layer PPCs, which were recently studied. Furthermore, it was shown that the proposed method can be implemented with approximately 1% of the whole circuit of a PPC.

Academic Significance and Societal Importance of the Research Achievements

本研究成果により，これまで1Tbps程度の処理速度が限界と見込まれていたインターネットルータのテーブル検索において，同程度の消費電力で1.5Tbps程度の処理速度を実現できることが示された．また，提案機構をハードウェア実装する際のハードウェアコスト量についても明らかとなった．本研究成果が波及することで，1Tbps以上の処理速度を備えたルータをこれまでよりも低コストに実現することが期待できる．

Research Products

• [Journal Article] RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache (2020)
  • Author(s): Yamaki Hayato、Nishi Hiroaki、Miwa Shinobu、Honda Hiroki
  • Journal Title: IEICE Transactions on Information and Systems Volume: E103.D Issue: 12 Pages: 2590-2599
  • DOI: 10.1587/transinf.2020EDP7035
  • NAID: 130007948506
  • ISSN: 0916-8532, 1745-1361
  • Year and Date: 2020-12-01
  • Peer Reviewed
• [Journal Article] Effective cache replacement policy for packet processing cache (2020)
  • Author(s): Yamaki Hayato
  • Journal Title: International Journal of Communication Systems Volume: 33 Issue: 14
  • DOI: 10.1002/dac.4526
  • Peer Reviewed
• [Journal Article] Hybrid Memory Design for High-Throughput and Low-Power Table Lookup in Internet Routers (2020)
  • Author(s): Yamaki Hayato
  • Journal Title: International Journal of Advanced Computer Science and Applications Volume: 11 Issue: 6 Pages: 61-69
  • DOI: 10.14569/ijacsa.2020.0110608
  • Peer Reviewed
• [Journal Article] Efficient Cache Architecture for Table Lookups in an Internet Router (2020)
  • Author(s): Yamaki Hayato
  • Journal Title: International Journal of Advanced Computer Science and Applications Volume: 11 Issue: 5 Pages: 664-672
  • DOI: 10.14569/ijacsa.2020.0110581
  • Peer Reviewed
• [Presentation] Routing/ARP/ACL/QoSごとのテーブル分離パケット処理キャッシュ (2021)
  • Author(s): 長田大樹，田中京介，八巻隼人，三輪忍，本多弘樹，五島正裕
  • Organizer: 情報処理学会研究報告 2021-ARC-244
• [Presentation] Efficient Cache Architecture for Packet Processing in Internet Routers (2020)
  • Author(s): Hayato Yamaki
  • Organizer: 2020 Future of Information and Communication Conference (FICC 2020)
  • Int'l Joint Research
• [Presentation] Multi-Level Packet Processing Caches (2019)
  • Author(s): Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa and Hiroki Honda
  • Organizer: IEEE Symposium on Low-Power and High-Speed Chips and Systems
  • Int'l Joint Research
• [Presentation] 1Tbps実現に向けたルータのメモリ階層の最適化 (2018)
  • Author(s): 田中京介，八巻隼人，三輪忍，本多弘樹
  • Organizer: 第225回システム・アーキテクチャ研究発表会